【Principles of Computer Composition】Reset version of final review questions

written in front

The content is exactly the same as https://blog.csdn.net/qq_46640863/article/details/124998142
. But this article is not a handwritten version.

Chapter One

1. The main frequency of a computer is 4MHz, and the average execution time and usage frequency of various instructions are shown in the table below. Then the machine MIPS is $\underline{0.5}$, CPI is $\underline{8}$
$$\begin{array}{ccccc}command\; type& access& Addition,\; subtraction,\; comparison,\; transfer& multiply\; and\; divide& other\\ average\; execution\; time& 1.0\mu s\_& 0.5\mu s& 10ms& 2.5\mu s\\ & 30\%& 40\%& 10\%& 20\%\end{array}$$
The total average time of a single instruction: $1.0\ast 30\%+0.5\ast 40\%+10\ast 10\%+2.5\ast 20\%=2\mu s$
$$\begin{gathered} MIPS=\frac{}{time}=\frac{1(one\; command}{2\times 10^{-6}\times 10^6}=0.5 \\ CPI=\frac{}{MIPS\ast 10^6}=\frac{4\ast 10^6}{0.5\ast 10^6}=8 \end{gathered}$$

2. Suppose computer $M_1$and $M_2$With the same instruction architecture, the main frequency is 1.5GHz and 1.2GHz respectively, in $M_1$and $M_2$Run program P on , the average CPI is 2 and 1 respectively, then the running time ratio of program 1 and 2 is
$$\frac{\frac{1}{1.5GHz}\times 2}{\frac{1}{1.2GHz\_}\times 1}=\frac{8}{5}$$

3. What is the basic idea of ​​von Neumann computer architecture? main idea?

(1) Binary is used; (2) program is stored, and the instruction is stored in the memory, and the instruction controls the computer. (core idea); (3) It consists of five components: arithmetic unit, memory, controller, input and output.

Chapter two

1. Assuming that the number of a certain machine is 10001000, write out the decimal numbers corresponding to the original code, inverse code, and complement code respectively.

Original code: -8

Inverse code: corresponding to the original code 1111 0111, true value -119

Complementary code: corresponding to the original code 1111 1000, true value -120

2. There are the following C language statements

short s=-32767;
unsigned us=s;

After executing the above statement, what is the value of us?

s original code: 1111 1111 1111 1111

s complement: 1000 0000 0000 0001 (derived from -32768's complement is 1000 0000 0000 0000)

us=s, us original code=s complement code=1000 0000 0000 0001

us=32769

3. The float data is represented by IEEE 754 single precision, assuming that two floats X and Y are stored in the 32-bit register $F_1$,$F_2$In, $F_1$=CC90 0000H,$F_2$=B0C0 0000H, what is the relationship between X and Y?

$F_1=CC900000H=1\underline{10011001}\overline{00100000000000000000000}$

Then the symbol is 1, the order code (offset 127) is 153, and the value bit is 1.001

$F_1=(1.001{)}_2\times 2^{26}=-\frac{9}{8}\times 2^{26}$

$F_2=B0C00000H=1\underline{01100001}\overline{10000000000000000000000}$

Then the symbol is 1, the order code (offset 127) is 97, and the value bit is 1.1

$F_2=(1.1{)}_2\times 2^{-30}=-{\frac{3}{2}}^{-30}$

$F_1<F_2$

4. Write the IEEE 754 floating-point encoding of -5

$5=(101{)}_2=1.01\times 10^{(10{)}_2}$

sign bit: 1

Step code offset: 2+127=129=1000 0001

$1\underline{10000001}\overline{01000000000000000000000}$

C0A0 0000

5. Put $\frac{67}{128}$Expressed as a floating point number

128 has 7 digits, so it can be represented with 7 decimal places.

$(67{)}_{10}=(01000011{)}_2$

$(\frac{67}{128}{)}_{10}=0.100011=1.000011\times 10^{-1}$

$0\underline{01111110}\overline{00001100000000000000000}$

3F060000

third chapter

1. Set the machine word length to 8 bits (including a sign bit), and use complement code addition and subtraction to calculate $[X-Y{]}_{}$, restore the result to the true value, and explain what SF, OF, ZF, and CF in PSW are. where, X=-65,Y=78
$$\begin{gathered} X=X_{n-1}...X_0 \\ Y=Y_{n-1}...Y_0 \\ S=X\mathrm{op}Y=S_n{S}_{n-1}...S_0 \end{gathered}$$
$OF$ is used to judge complement overflow, which requires double sign bit judgment

$CF=S_n$;

$SF=S_{n-1}$

$ZF=\overline{S_{n-1}+S_{...}+S_0}$

Then $X=(-65{)}_{10}=10111111$；$Y=(78{)}_{10}=01001110$

$-Y_{}$为$Y$ is reversed together with the sign bit + 1=1011 0010

$[X{]}_{}+[-Y{]}_{}=10111111+10110010=101110001$

So, CF=1, SF=0, ZF=0.

Restore 0111 0001 to the true value 113

OF: Double sign bit judgment. The result of the double-sign bit operation does not look at the highest bit, but only the 2/3 bit.

$X=1101111111$

$-Y=110110010$

$X-Y=1\underline{10}1110001$

Negative overflow occurs, then OF=1

2. Set the length of the floating-point number to 12 bits, 4 digits of the exponent code (2 digits of the exponent character), 8 digits of the mantissa (2 digits of the end character), and the form of the machine number is self-determined (the exponent code can be positioned before the mantissa), press Floating-point addition and subtraction $[X+Y{]}_{}$,$X=0.110101\times 2^{-01},Y=-0.100101\times 2^{+01}$

$$\begin{gathered} X=0.110101\times 2^{-01} \\ Y=-0.100101\times 2^{+01} \end{gathered}$$

For order: (01)-(-01)=2, X is shifted to the right by 2 bits to become $X=0.001101\times 2^{01}$

0.0000 1101+0.1110 0101=0.1111 0010
$$0.11110010\times 2^{0001}$$

3. A word length 8-bit addition and subtraction operation circuit is shown in the figure

(1) Suppose dst=86H, src=F6H, control op0~op3 for subtraction, F=? FLAG=?

$o{p}_{3\sim 0}=1010$

dst=1000 0110,src=1111 0110

F=dst-src=0 1001 0000

CF=0, SF=1, ZF=0, double symbol calculation is 01 1001 0000, OF=0

(2) If the above two operands are unsigned numbers, what is the decimal value? What is the basis for judging overflow? Does it overflow?

144 CF judging overflow, overflow. (CF=0 in unsigned subtraction means overflow, CF=1 means no overflow)

(3) If the two operands are signed numbers, what is the decimal value? How to judge whether it overflows?

-112 OF does not overflow

4. Suppose an 8-bit word length computer runs the following C program segment

unsigned int x = 134;
unsigned int y = 246;
int m = x;
int n = y;
unsigned int z1 = x-y;
unsigned int z2 = x+y;
int k1 = m-n;
int k2 = m+n;

Suppose the compiler will $R_1\sim R_8$assigned to x,y,m,n,z1,z2,k1,k2

(1) After executing the above program segment, $R_1,R_5,R_6$What are the contents?

$R_1=X=10000110=86H$

y=1111 0110, $(-y_{})$=0000 1010,$R_5$=x-y=1001 0000=90H,$R_6$=x+y=0111 1100=7CH

(2) What are the values ​​of m and k1 respectively?

m=x= $(10000110{)}_{}$=-122

k1=mn= $(10010000{)}_{}$=-112

(3) The above program segment involves addition and subtraction of signed integers and unsigned integers. Can the same kind of adder and auxiliary circuit be used?

able

(4) How does the computer determine whether the addition and subtraction of signed integers overflows? Which signed number execution results overflow?

OF state, k2 overflows.

chapter Five

1. There is a memory with 14-bit address and 8-bit data
(1) What is the capacity of this memory?
(2) If the memory is composed of 1K*1 memory chips, how many chips are needed?
(3) Which addresses need to be used to decode the chip selection?

(1)
$$2^{14}\times 2^8=2^{22}=4M$$
(2)

Bit extension: $\frac{8}{1}=8$

Word expansion: $\frac{2^{14}}{2^{10}}=2^4=16$

16*8=128

(3)
$$A_{13}{A}_{12}{A}_{11}{A}_{10}$$
2. A memory capacity is 4KB, ROM is 2KB, choose 2K $\times 8$ ROM chip; RAM is 2KB, choose 1K$\times 8$ RAM chips, draw the storage structure of the main memory

1 piece of ROM, 2 pieces of RAM, word expansion

ROM address:
$$11bitson\; chip\{\begin{array}{l}0|00000000000\\ 0|11111111111\end{array}$$
RAM address:
$$10bitson\; chip\{\begin{array}{l}RA{M}_1\{\begin{array}{l}10|0000000000\\ 10|1111111111\end{array}\\ RA{M}_2\{\begin{array}{l}11|0000000000\\ 11|1111111111\end{array}\end{array}$$
$ROM=\overline{A_1}$,
$RA{M}_1=A_{11}\overline{A_{10}}$
$RA{M}_2=A_{11}{A}_{10}$

Chapter Six

1. The word length of a certain machine is 32 bits, and the instruction is a single-word instruction. There are several two-address instructions, one-address instructions and zero-address instructions in the system. It is known that each address code is 12 bits long, and the extended operation code method is used, how many two-address instructions and one-address instructions are at most?
$$\begin{array}{ccc}OP& address1& address2\\ 8& 12& 12\end{array}$$
Two-address instruction: $2^8-1=255$
One-address instruction: Assuming there is only one two-address instruction, then one-address instruction$255\ast 2^{12}-1$ _

2. The main memory is addressed by byte, the address is 7EA8H as the first address to store a two-byte instruction, the first one is the operation code OP is a transfer instruction, the second byte is relative addressing, the displacement is D, which is a 8-bit complement code
1. The displacement amount D represents the range?
-128~+127
2. The command transfer space?
7EA8H is the first address, the operation code +2 is 7EAA
7EAA-128=7E2A
7EAA+127=7F29
3. A computer adopts 16-bit fixed-length instruction word format, and designs 3 conditional transfers (N is a symbol flag)
$$\begin{array}{ccccc}15\sim 11& 10& 9& 8& 7\sim 0\\ 00000& C& Z& N& OFFSET\end{array}$$
00000 is op, CZN is CF, ZF, NF detection bit, if a certain detection bit is 1, it will detect the corresponding bit, if one of CF, ZF, NF is 1, it will transfer, OFF is the relative offset, and the target address (PC) when $(PC)+2+2\times OFFSET$ , when executing sequentially$\left(PC\right)+2$

(1) The address of a conditional transfer instruction is 200CH, if CF=0, ZF=0, NF=1 when the instruction is executed, what is the PC value after execution? If CF=1, ZF=0, NF=0 during execution, what is the value of PC?
$$\begin{array}{ccccc}15\sim 11& 10& 9& 8& 7\sim 0\\ 00000& 0& 1& 1& 11100011\end{array}$$
NF=1,
OFFSET=1110 0011=1111 1111 1110 0011=FFE3
PC=200C+2+2*FFE3=1FD4
CF=1, ZF=0, NF=0, do not transfer. 200C+2=200E

(2) What should CZN be to achieve transfer when unsigned numbers are compared less than or equal to?

Z=1,C=1

Chapter VII

1. The instruction DEC(100H) is a minus 1 instruction, and the operand addressing mode is indirect addressing
$$\begin{array}{cc}0000H& 1000H\\ 1000H& 2000H\\ 2000H& 0000H\end{array}$$

(1) What is the instruction operand?
0000H

(2) How many times does DR change during the instruction cycle?
5

(3) The execution of the instruction is completed, DR =FFFF

(4)SOCZ
1000

Fetch instruction, change once DR
fetch 1000H, change once
fetch 2000H, change once
fetch 0000H, change once
execute 0000H, FFFH->DR

2. A CPU with a main frequency of 1.03GHz adopts a 4-stage instruction pipeline, and each pipeline requires 1 clock cycle to execute. Assuming that the CPU executes 100 instructions without blocking, what is the throughput rate?
$$TP=\frac{n}{kT+(n-1)T}=\frac{100}{(4+99)\frac{1}{main\; frequency}}=1\times 10^9$$
3. A computer uses a micro-program controller, and the micro-operation control field is directly coded, with a total of 33 micro-commands. 5 mutex classes, including 7,3,12,5,6 microcommands respectively. How many bits are required for the control field?
$$\begin{array}{ccccc}7& 3& 12& 5& 6\\ 3& 2& 4& 3& 3\end{array}$$
3+2+4+3+3=15

4. In the five functional segment instruction pipelines, assuming that the execution time of each segment is 10ns, 8ns, 10ns, 10ns, 7ns, what is the speedup ratio for the 12 instruction pipelines? What is the actual throughput rate?
$$\begin{gathered} S_p=Speedup\; ratio=\frac{No\; pipeline}{Pipeline\; time}=\frac{nkT}{kT+(n-1)T}=3.375 \\ T=\underset{i}{\max }{T}_i=\max (T_1,T_2,...,T_n) \\ {T}_p=\frac{n}{kT+(n-1)T}=\frac{12}{10\times 5+11\times 10}=0.075 \end{gathered}$$

chapter eight

1. The main memory-cache adopts direct image, the block size is 32B, the cache unit is 4 blocks, and the main memory capacity is 64 blocks

(1) Draw main memory and cache address format
$$\begin{array}{cccccc}area\; code& block\; number& block& & cacheblock\; number& block\; address\\ 4& 2& 5& & 2& 5\end{array}$$
(2) If there is no data in the cache at the beginning, the CPU reads 21H, 23H, 05H, 3FH, 63H, and 82H in sequence (the memory is coded by byte), writes out the area code and block number, and the contents of the address conversion table?

21H: 000 0010 0001, for the first time, the tag in block 01 of the address conversion table is 0000
23H: 000 0010 0011, hit, the tag in block 01 of the address conversion table is 0000
05H: 000 0000 0101, for the first time, the tag in block 00 of the address conversion table is 0000
3FH: 000 0011 1111, hit, the tag in block 01 of the address translation table is 0000
63H: 000 0110 0011, the first time, the tag in block 11 of the address translation table is 0000
82H: 000 1000 0010, no hit, the tag in address translation table 00 is 0001

hit rate $\frac{1}{3}$

Address conversion table
$$\begin{array}{cc}address\; translation\; tabletag& block\; number\\ 1& 00\\ 0& 01\\ x& 10\\ 0& 11\end{array}$$
2. The main memory-high-speed buffer adopts a fully associative image, the block size is 32B, the cache has 4 blocks, and the main memory capacity is 64 blocks

(1) Draw the address format of the main memory and cache address
$$\begin{array}{ccccc}Main\; memory\; block\; number& block\; address& & cacheblock\; number& block\; address\\ 6& 5& & 2& 5\end{array}$$
(2) There is no data in the cache at the beginning, and the empty cache blocks are loaded in order from small to large when loading, and the cache is replaced by FIFO. If the CPU reads 21H, 23H, 05H, 3FH, 63H, 82H in sequence, and writes the block number, these operations After completion, what are the contents of the 4 units of the address translation table?

21H: 0010 0001
23H: 0010 0011 hit
05H: 0000 0101
3FH: 0011 1111 hit
63H: 0110 0011
82H: 1000 0010
hit $\frac{1}{3}$
$$\begin{array}{cc}tag& block\; number\\ 001& 00\\ 000& 01\\ 011& 10\\ 100& 11\end{array}$$

Chapter nine

1. Suppose a computer has four levels of interrupts ABCD and hardware queuing priority ABCD. The following table shows the time required to execute each level of interrupt service routine. The time of executing the interrupt service routine is used as the basis for interrupt processing priority. The shorter the time, the priority Higher
$$\begin{array}{ccccc}program& A& B& C& D\\ & 5\mu s& 15\mu s& 3\mu s& 12\mu s\end{array}$$
(1)Specify
$$\begin{array}{ccccc}& A& B& C& D\\ A& 1& 1& 0& 1\\ B& 0& 1& 0& 0\\ C& 1& 1& 1& 1\\ D& 0& 1& 0& 1\end{array}$$
(2) If ABCD are respectively in 6 $\mu s$ ,8$\mu s$ ,10$\mu s$ ,0s issue an interrupt request, draw the execution sequence

2. Interrupts are used between the CPU and the peripherals to realize data input and output. The connection method is as shown in the figure

(1) What are the valid conditions for INTA?

CPU enables interrupts

(2) Interrupt response priority from high to low?

2->3->4->1

(3) If the order of interrupt nesting processing priority from large to small is 4231, then 3 mask words?

1010

(4) How many problems need to be solved in the interrupt response cycle?

After the CPU responds to the request INTR, the interrupt mechanism is answered by INTA.
The interrupt mechanism sends the vector address VA with the highest interrupt priority to the CPU.
The CPU pushes the current PC and PSW on the stack for protection.
According to the vector address, the interrupt vector is taken out from the interrupt vector table in the memory and sent to the PC, and the interrupt is turned off.
A hardwired controller takes several machine cycles for the interrupt response period.

3. There are 104 signal lines in a bus, including 32 data lines, 25 address lines, 47 control lines, and a working frequency of 33MHz. What is the bus width? transmission rate?

32bit，$\frac{32}{8}\times 33M\_=132MB/s$

4. Combining the query method to input the interface circuit, explain the data transmission process between the CPU and peripherals

When the input device is ready for data, send the data into the data register, generate a pulse signal STB, latch the input data into the data register, and set the Ready position of the status register to 1.

The CPU detects the status word, reads the status word first, and checks whether the Ready bit is 1. If Ready=1, then execute step 2: read data from the data port, and set Ready to 0

5. A computer instruction is divided into 4 functions: IF, ID, EXE, WR, assuming that the time of each function is 90ns, 80ns, 70ns, 60ns

(1) The CPU clock cycle is at least?
90ns

(2) If the adjacent instruction data is related, how many clock cycles will the latter instruction be delayed?
$$\begin{array}{ccccccc}IF& ID& EX& WR& & & \\ & block& block& IF& ID& EX& WR\\ & IF& & & ID& EX& WR\end{array}$$
(Both blocking and instruction fetching methods are available)

(3) If the adjacent instruction data is related, what measures can be taken in order not to delay the next instruction?

$\frac{32}{8}\times 33M\_=132MB/s$

4. Combining the query method to input the interface circuit, explain the data transmission process between the CPU and peripherals

When the input device is ready for data, send the data into the data register, generate a pulse signal STB, latch the input data into the data register, and set the Ready position of the status register to 1.

The CPU detects the status word, reads the status word first, and checks whether the Ready bit is 1. If Ready=1, then execute step 2: read data from the data port, and set Ready to 0

5. A computer instruction is divided into 4 functions: IF, ID, EXE, WR, assuming that the time of each function is 90ns, 80ns, 70ns, 60ns

(1) The CPU clock cycle is at least?
90ns

(2) If the adjacent instruction data is related, how many clock cycles will the latter instruction be delayed?
$$\begin{array}{ccccccc}IF& ID& EX& WR& & & \\ & block& block& IF& ID& EX& WR\\ & IF& & & ID& EX& WR\end{array}$$
(Both blocking and instruction fetching methods are available)

(3) If the adjacent instruction data is related, what measures can be taken in order not to delay the next instruction?

Forwarding, bypassing (establishing a dedicated data path, and directly inputting the result of the register operation to the ALU)