0. Front
Abstract Model Hierarchy:
• System level: A model that implements the external capabilities of a design module using high-level language constructs.
• Algorithm: A model that implements a design algorithm using high-level language constructs.
• RTL Level (Register Transfer Level): A model that describes the flow of data between registers and how to process these data.
• Gate-level: A model describing logic gates and connections between logic gates.
• Switch-level: A model describing the transistors and storage nodes in the device and the connections between them.
1. The most basic data type
reg type, wire type, integer type, parameter type
In digital circuits, x represents an indeterminate value, and z represents a high resistance value .
A number can be defined as a negative number by adding a minus sign before the bit-width expression. The minus sign must be written at the top of the number definition expression.
When changing the parameters of one module in another module, you need to use the defparam command.
Wire data is often used to represent combinatorial logic signals specified with the assign keyword.
The reg type data is often used to represent the specified signal used in the "always" module , often representing a flip-flop.
The default initial value of reg data is indeterminate .
The memory type data is generated by extending the address range of the reg type data. Example:
reg [n-1:0] mema[m-1:0];
This example defines a memory named mema that has m n-bit memories.
Note : Expressions that address memory must be constant expressions.
To read and write a storage unit in memory, the address of the unit in the memory must be specified. The following writing is correct:
mema[3]=0; //Assign 0 to the third storage unit in memory.
2. Operators and Expressions
1) Arithmetic operators (+,-,×,/,%)
2) Assignment operators (=,<=)
3) Relational operators (>,<,>=,<=)
4) Logical operators (&& ,||,!)
5) Conditional operator (?:)
6) Bitwise operator (~,|,^,&,^~):
a) ~ //inverse
b) & //bitwise AND
c) | //Bitwise OR
d) ^ //Bitwise exclusive OR
e) ^~ //Bitwise exclusive OR (XOR NOT)
7) Shift operator (<<,>>)
8) Concatenation operator ({ })
9) Others:
reduction operator: For example:
reg [3:0] B;
reg C;
C = &B;
is equivalent to:
C =( (B[0]&B[1]) & B[ 2] ) & B[3];
3. Keywords
4. Assignment Statements and Block Statements
1) Assignment statement
In Verilog HDL language, there are two assignment modes for signals:
(1). Non-blocking (Non_Blocking) assignment mode (such as b <= a; )
1) The assignment operation is completed after the end of the block.
2) The value of b does not change immediately.
3) This is a relatively common assignment method. (Especially when writing synthesizable modules)
(2). Blocking assignment method (such as b = a; )
1) After the assignment statement is executed, the block ends.
2) The value of b changes immediately after the assignment statement is executed.
3) Unexpected results may occur.
2) Block Statements
Block statements are usually used to combine two or more statements to make them look more like one statement in format. There are two types of block statements, one is the begin_end statement, which is usually used to identify the statements to be executed in sequence, and the blocks identified by it are called sequential blocks. One is the fork_join statement, which is usually used to identify statements to be executed in parallel, and the block identified by it is called a parallel block.
a) Sequence block
The sequence block has the following characteristics:
1) The statements in the block are executed in sequence, that is, only the following statement can be executed after the execution of the above statement.
2) The delay time of each statement is relative to the simulation time of the previous statement.
3) The program flow control does not jump out of the block until the last statement is executed.
The format of a sequence block is as follows:
begin
statement 1;
statement 2;
...
statement n;
end
b. Parallel block
Parallel block has the following four characteristics:
1) The statements in the block are executed at the same time, that is, as soon as the program flow control enters the parallel block, the statements in the block start to be executed simultaneously and in parallel.
2) The delay time of each statement in the block is relative to the simulation time when the program flow control enters the block.
3) Delay time is used to provide execution timing for assignment statements.
4) When the last statement is executed or a disable statement is executed according to the time sequence, the program flow control jumps out of the program block.
The format of the parallel block is as follows:
fork
statement1;
statement2;
......
statementn;
join
5. Conditional Statements
1) if_else statement
The if statement is used to determine whether the given condition is satisfied, and according to the result of the determination (true or false), it is decided to execute one of the two operations given.
Verilog HDL language provides three forms of if statement.
(1).if(expression) statement
(2).if(expression) statement 1
else statement 2
(3).if(expression 1) statement 1;
else if(expression 2) statement 2;
else if( expression 3) statement 3;
........
else if(expression m) statement m;
else statement n;
If it is 0,x,z, it is processed as "false", if it is 1, it is processed as "true"
2) case statement
The case statement is a multi-branch selection statement. The if statement has only two branches to choose from. However, multi-branch selection is often used in practical problems. The case statement provided by Verilog language directly handles multi-branch selection. The case statement is usually used for instruction decoding in microprocessors, and its general form is as follows:
1) case (expression) <case branch item> endcase
2) casez (expression) <case branch item> endcase
3) casex (expression Formula) <case branch item>
The general format of the endcase case branch item is as follows:
branch expression: statement
Default item (default item): statement
The casez statement is used to handle the comparison process without considering the high resistance value z, and the casex statement will Both high resistance z and indeterminate values are considered do not care situations.
Unexpected latches are generated in the design due to improper use of conditional statements: if you use an if statement, it is best to write an else item. If you use a case statement, it is best to write the default item. Following the above two principles, you can avoid this kind of error, make the designer more clear about the design goal, and also enhance the readability of the Verilog program.
6. Loop Statement
Four types of loop statements are used to control the number of times the statement is executed.
1) forever executes statements continuously.
2) repeat executes a statement n times consecutively.
3) while executes a statement until a certain condition is not met. If the initial condition is not met (is false), the statement cannot be executed once.
4) for determines the loop execution of the statement through the following three steps.
a) First assign an initial value to the variable that controls the number of loops.
b) Determine the value of the expression that controls the loop. If it is false, jump out of the loop statement. If it is true, execute the specified statement and go to the third step.
c) Execute an assignment statement to modify the value of the variable that controls the number of times the loop variable is returned, then return to step 2.
7. Structural declarative statements
Any procedure module in Verilog language is subordinate to the declarative statements of the following four structures.
1) initial statement
2) always statement
3) task statement
4) function statement
8. Compile preprocessing
1) The macro definition `define
uses a specified identifier (namely) to represent a string, and its general form is:
`define identifier (macro name) string (macro content)
2) "file inclusion" processing `include
The so-called "file inclusion" processing is that a source file can include the entire contents of another source file, that is, another file is included in this file. The Verilog HDL language provides the `include command to implement the "file inclusion" operation. Its general form is:
`include "filename"
"file include" command is very useful, it can save the programmer's repetitive work. You can combine some commonly used macro definition commands or tasks into a file, and then use the `include command to include these macro definitions into the source file you write, which is equivalent to using standard components in the industry.
3) Time scale `timescale`
The timescale command is used to specify the time unit and time precision of the module following the command. The format of the `timescale command is as follows:
`timescale<time unit>/<time precision>
In this command, the time unit parameter is used to define the base unit of the simulation time and delay time in the module.
4) Conditional compilation commands `ifdef, `else, `endif
Conditional compilation commands have the following forms:
1) `ifdef macro name (identifier)
block 1
`else
block 2
`endif
Its function is when the macro name has been If it has been defined (defined with the `define command), the program segment 1 will be compiled, and the program segment 2 will be ignored; otherwise, the program segment 2 will be compiled, and the program segment 1 will be ignored.
2) `ifdef macro name (identifier)
block 1
`endif
The syntax of Verilog HDL has many similarities with the syntax of C language, but there are also many differences.