[Reference material]: STM32F4xx Chinese Reference Manual & STM32F4 Development Guide (Punctual Atom)
Fundamental
SPI is the abbreviation of (Serial Peripheral Interface), a synchronous serial interface technology, which is a high-speed, full-duplex, and synchronous communication bus .
SPI is a serial synchronization protocol. Data is transmitted bit by bit. SCK provides clock pulses. MOSI and MISO complete data transmission on the basis of pulses.
Disadvantages: no specified flow control, no response mechanism to confirm whether data is received
Pin function
It can work in master-slave mode, one master device can connect multiple slave devices, at least 4 wires are required
MOSI: master device output, slave device input
MISO: main device input, slave device output
SCLK: clock signal, generated by the master device, when there is no clock jump, the slave device does not collect or transmit data
CS: Chip selection signal. When multiple devices are connected to one SPI bus, the CS of SPI itself can be replaced by other I/O port pins, and the CS end of each slave device can be connected to different GPIO port pins.
Data sending and receiving process
Buffer zone
In the receiving process, after the data is received, it is first stored in the internal receiving buffer ; while in the sending process, the data is first stored in the internal sending buffer, and then the data is sent .
The read access to the SPI_DR register will return the receive buffer value; the write access to the SPI_DR register will store the written data in the transmit buffer.
Start communication sequence in master mode
In full duplex mode
When writing data to the SPI_DR register (transmit buffer) in full duplex mode (BIDIMODE=0 and RXONLY=0) , the communication sequence starts. Then during the first bit transmitted , from the transmission buffer and the data line is loaded into the 8-bit shift register (for loading in parallel, meaning that the first data bit begins a transmission, the transmission buffer is empty, TXE flag bit 1), and then move it out to the MOSI pin in a serial manner.
At the same time, the data received on the MISO pin is serially shifted into the 8-bit shift register, and then loaded into the SPI_DR register (receive buffer) in parallel .
Handle sending and receiving
During the transmission of the first bit, when data is transferred from the transmit buffer to the shift register, the TXE flag (transmit buffer is empty) is set to 1 . This flag indicates that the internal transmit buffer is ready to load the next data. If the TXEIE bit in the SPI_CR2 register is set, an interrupt can be generated. Clear the TXE bit by writing to the SPI_DR register.
Note : The software must ensure that the TXE flag is set before attempting to write to the transmit buffer . Otherwise, the data previously written to the send buffer will be overwritten
When transferring data from the shift register to the receive buffer, the RXNE flag (the receive buffer is not empty) will be set to 1 on the last sampling clock edge . It indicates that it is ready to read data from the SPI_DR register. If the RXNEIE bit in the SPI_CR2 register is set, an interrupt can be generated. Clear the RXNE bit by reading the SPI_DR register
SPI communication mode
Emphasize: the master and slave must work in the same mode to communicate normally
| mode | CPOL clock polarity | CPHA clock phase |
|---|---|---|
| MODE0 | 0 | 0 |
| MODE1 | 0 | 1 |
| MODE2 | 1 | 0 |
| MODE3 | 1 | 1 |
- CPOL=0, it means that it is in idle state when SCLK=0, and the effective state is when SCLK is at high level
- CPOL=1, it means that it is in idle state when SCLK=1, and the effective state is when SCLK is in low level
- CPHA=0, which means that the data is sampled on the first edge, and the data is sent on the second edge
- CPHA=1, which means that the data is sampled on the second edge, and the data is sent on the first edge
-
CPOL=0, CPHA=0: In the idle state, SCLK is at low level, and data sampling is on the first edge, that is, the transition of SCLK from low to high, so data sampling is rising Edge, data transmission is on the falling edge.
-
CPOL=0, CPHA=1: At this time, in idle state, SCLK is at low level, data transmission is on the second edge, that is, SCLK transitions from low level to high level, so data sampling is falling Edge, data transmission is on the rising edge.
-
CPOL=1, CPHA=0: In the idle state, SCLK is at high level, and data collection is on the first edge, that is, the transition of SCLK from high level to low level, so data collection is falling Edge, data transmission is on the rising edge.
- CPOL=1, CPHA=1: At this time, in idle state, SCLK is at high level, and data transmission is on the second edge, that is, the transition of SCLK from high to low, so data collection is rising Edge, data transmission is on the falling edge.
When CPHA is equal to 0, data is always sampled on odd edges, as shown in the figure above
When CPHA is equal to 1, the data is always sampled on the even-numbered edge of SCK, as shown in the figure above
Explanation : The communication clock is initiated by the master device. The sending data of the master and the slave are completed at the same time, and the receiving data of both are also completed at the same time. That is, when the master sends data on the rising edge, the slave also sends data.
In order to ensure that the master and slave can communicate correctly, the SPI of both should have the same clock polarity and clock phase, that is, both must work in the same mode
SPI status flag
- Transmit buffer is empty (TXE)
This flag bit is 1, indicating that the sending buffer is empty, and the next data to be sent can be sent to the buffer. Write to the SPI_DR register will clear the TXE flag
- The receive buffer is not empty (RXNE)
When this flag is set to 1, it indicates that there is valid received data in the receive buffer. Read the SPI_DR register, the flag bit will be cleared
- BUSY
The BSY flag is set and cleared by hardware (writing to this flag has no effect). The BSY flag is used to indicate the status of SPI communication.
When BSY is set to 1, it indicates that the SPI is busy communicating. There is an exception in the two-way communication receiving mode (MSTR=1 and BDM=1 and BDOE=0) in the master mode. The BSY flag remains low during the receiving process.
If the software wants to close the SPI and enter the stop mode (or turn off the peripheral clock), the BSY flag can be used to detect the end of the transfer to avoid destroying the last data transfer.
Note : Do not use the BUSY flag to process each data transmission or reception, it is better to use the TXE flag and RXNE flag instead
Close SPI
To turn off SPI, it is recommended to perform the following steps in master mode or full-duplex slave mode (BIDIMODE=0, RXONLY=0):
- Wait for RXNE=1 to receive the last data
- Wait for TXE=1
- Then wait for BSY=0
- Turn off SPI (SPE=0), and finally enter stop mode (or turn off peripheral clock)
Use DMA for SPI communication
When the enable bit in the SPI_CR2 register is enabled, DMA access will be requested. Send buffer and receive buffer will issue their own DMA request
- During the transmission process, a DMA request will be issued every time the TXE bit is set . DMA then performs a write operation to the SPI_DR register (this operation will clear the TXE flag)
- During the receiving process, a DMA request will be issued every time the RXNE bit is set . DMA then reads the SPI_DR register (this operation will clear the RXNE flag)
In the transmit mode, after the DMA has completed the transmission of all data to be sent (the TCIF flag in the DMA_ISR register is set to 1), the BSY flag can be monitored to ensure that the SPI communication has been completed. This step must be performed before closing the SPI or entering the stop mode to avoid damage to the last data transmission. The software must first wait for TXE=1, and then wait for BSY=0
Note: I don’t understand the flow of the DMA transmission and reception sequence diagram here. You need to go back to the front to understand the process of processing data transmission and reception-part of the content