Original Address :: http://blog.gpjtag.com/?p=643
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3, STM32F4 series MCU SPI2 problem ---- http://www.openedv.com/posts/list/62106.htm
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Recently SPI2 need to use SPI1 and work together to get hold of two of SPI communication:
Hardware wiring as follows:SPI1.SCK -> DEV.SCK
SPI1.SCK -> SPI2.SCK
SPI1.MOSI -> DEV.MOSI[0]
SPI1.MISO <- DEV.MISO[0] SPI2.MISO -> DEV.MOSI[1]
SPI2.MOSI <- DEV.MISO[1]
The SPI1 set to Master mode, set the SPI2 Slave.
Set CPOL = 0, CPHA = 0 (that is not transmitted when the clock is low, the sampling rising edge, the falling edge of the data update).
The specific configuration is not affixed, there is the example stm32fwlib inside.
Note: The official use of the Internet and configurations are SPI1 is Slave, SPI2 for the Master! Next would say.
Problems encountered introduction: SPI1 correct data SPI2 get is a mess ......
Separate the SPI1 set to Master and FPGA communication is found in the normal maximum speed 18Mhz, I began to wonder whether there SPI2 the Bug ......
then separate the SPI1 and SPI2 loopback test:SPI1.SCK -> SPI2.SCK
SPI1.MOSI -> SPI2.MOSI
SPI1.MISO <- SPI2.MISO
And transmitting the random number received, we find SPI1 and SPI2 the received data is not normal, but differentiated
- After sending the SR SPI1 is 0x02 (TX empty)
- SPI2 the SR is 0x82,0x40 (0x80 is busy, 0x40 is overrun)
There are serious doubts SPI2 problem, busy not fully explained sending the data, overrun description after sending data over there before the clock result in washed away.
Try to GPIO and analog SPI1 SPI2 communication, problem, like, a little doubt whether to do the STM32 SPI Slave ............
Look at the official code, suddenly found that the official was SPI1 as Slave, and finally try to SPI1 set to Slave, SPI2 for the Master, normal! ! !SPI2.SCK -> SPI1.SCK
SPI2.MOSI -> SPI1.MOSI
SPI2.MISO <- SPI1.MISO
STM32 before I heard the film might have Bug, do SPI1 and SPI2 is not the same? After all, in most cases only a SPI1, rarely used the SPI2.
Internet search a bit errata, said the SPI2 Slave mode and USART3 there is a conflict, and I2S there will be a problem, so the first time lpc wanted to change the film, but the same functionality as expensive half, forget it.
Fixed: Today caught up with logic analyzer waveform.
This is SPI2 as Master, SPI1 as Slave.
This is SPI1 as Master, SPI2 as Slave.
Regardless of which you can see to do Master, the edge is right, but do SPI2 from when there are glitches ......
IDLE level sometimes the clock is not zero, or the suspect had STM32 problems, but suddenly see the hand as well as DuPont line, try to change a set of DuPont line, but still normal!
Test data correctly.(0) M_SR=02, S_SR=02, (MTX) 94ef == 94ef (SRX), (MRX) 53df == 53df (STX)
(1) M_SR=02, S_SR=02, (MTX) e746 == e746 (SRX), (MRX) e4ea == e4ea (STX)
(2) M_SR=02, S_SR=02, (MTX) 02f5 == 02f5 (SRX), (MRX) 006d == 006d (STX)
(3) M_SR=02, S_SR=02, (MTX) a3bc == a3bc (SRX), (MRX) 1728 == 1728 (STX)
(4) M_SR=02, S_SR=02, (MTX) 4b5b == 4b5b (SRX), (MRX) e7db == e7db (STX)
(5) M_SR=02, S_SR=02, (MTX) b192 == b192 (SRX), (MRX) 2f46 == 2f46 (STX)
(6) M_SR=02, S_SR=02, (MTX) b421 == b421 (SRX), (MRX) d829 == d829 (STX)
(7) M_SR=02, S_SR=02, (MTX) c6c8 == c6c8 (SRX), (MRX) ab44 == ab44 (STX)
(8) M_SR=02, S_SR=02, (MTX) e347 == e347 (SRX), (MRX) 7f57 == 7f57 (STX)
(9) M_SR=02, S_SR=02, (MTX) f95e == f95e (SRX), (MRX) e922 == e922 (STX)
But still can not understand why SPI1 able to communicate as a Slave, I also replaced the board and the new STM32 official line of DuPont, was also not used, in the end what happens ......
