RTL design (6)-pseudo-random number generator

Overview of pseudo-random numbers

Pseudo-random sequence, also known as pseudo-random code, is a group of artificially generated periodic sequences with a certain coding rule, and at the same time it is easy to repeatedly generate and process, so it is widely used in the field of communications. Usually the circuit that generates the pseudo-random sequence is a feedback shift register, which is divided into a linear feedback shift register and a nonlinear feedback shift register.

The binary number sequence with the longest period generated by the linear feedback shift register (LFSR) is called the maximum length linear feedback shift register sequence, or m sequence for short. The length of the shift register is n, then the period of the m sequence is 2 ⁿ -1 , There is no all-zero state.

The initial state of the pseudo-random number generator is given by the microprocessor or other modules through the seed. Seed cannot be all 0s , because 0^0=0, the module will fall into an endless loop of 0s.

Pseudo-random number generator

Design a pseudo-random number generator using LFSR.

randomgen.v

`timescale 1ns / 1ps

// Company: 
// Engineer: 
// 
// Create Date: 2020/12/13
// Author Name: Sniper
// Module Name: randomgen
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 


module randomgen(
    input clk,
    input rst_n,
    input load,
    input [7:0] seed,
    output reg [7:0] rand_num
);


always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		rand_num <= 0;
	else if(load)
		rand_num <= seed;
    else
        rand_num[7:0] <= {
    
    rand_num[6:0], rand_num[1] ^ rand_num[2] ^ rand_num[7]};
end


endmodule

tb_randomgen.v

`timescale 1ns / 1ps

// Company:
// Engineer:
//
// Create Date: 2020/12/13
// Author Name: Sniper
// Module Name: tb_randomgen
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//


module tb_randomgen;

//input
reg clk;
reg rst_n;
reg load;
reg [7:0] seed;


//output
wire [7:0] rand_num;



initial
begin
    clk = 0;
    rst_n = 0;
    load = 0;
    seed = 0;

	#100;
    rst_n = 1;

    @(posedge clk);
    seed <= 100;
    load <= 1;
    @(posedge clk);
    load <= 0;



end

//clock
always #5 clk = ~clk;



//DUT
randomgen DUT
(
    .clk(clk),
    .rst_n(rst_n),
    .load(load),
    .seed(seed),
    .rand_num(rand_num)
);

initial
begin
    $dumpfile("tb_randomgen.vcd");
    $dumpvars(0,tb_randomgen);
end

initial #1000 $finish;

endmodule

operation result

vcs -R randomgen.v tb_randomgen.v