In the author's old article Clock Gating's shallow views
, we discussed the method of tool processing gated clocks and the related benefits and area costs brought by gated clocks. In addition, the clock-gating check (clock-gating check) also has a corresponding processing method in STA. Through this article, let's learn about the relevant knowledge together, and will expand to some design suggestions for the clock network. Gossip less Say, ICer GO!
Classification of Gated Clocks
According to the different gating methods, a gating clock can usually be divided into the following base categories,
Active High (Active High) gated clock
It is usually implemented with an AND gate (and) or a NAND gate (nand).
When the enable signal is high, the clock can be released. If it is nand, the output clock is a reverse clock waveform
Active Low (Active High) gated clock
It is usually implemented using an AND gate (and) or a NAND gate (nand),
When the enable signal is low, the clock can be released. If it is nor, the output clock is a reverse clock waveform. In addition
to the above situation, sometimes a more complex clock gating structure is used. Here The waveform will be more complicated
Clock Gating for XOR Structure
When the enable signal is 1, the output is the reverse of the input, otherwise it is forward
Clock Gating for MUX Structures
Clock Propagation Monotonicity (unate)
The basic principle of static timing analysis is signal propagation. For propagation with clear monotonicity, it is the basis for constructing a correct STA environment. Data paths are usually not sensitive to monotonicity (unate), but clocks are usually edge-sensitive signals, so the monotonicity of the clock network Sex is particularly important in the form of STA timing analysis. The STA tool can only do correct timing analysis on the clock network with clear monotonicity , otherwise there is a high probability that there will be inconsistencies with STA in the actual chip. This is very important for the design of the clock network.
Through the above-mentioned several gating structures, from the perspective of monotonic clock (unate), it can be summarized as the following table
| gating structure | Monotonicity (unate) | category |
|---|---|---|
| AND | positive-unate | active high |
| NAND | negative-unate | active high |
| OR | positive-unate | active low |
| NOR | negative-unate | active low |
| XOR | positive-unate | when gated == 0 |
| XOR | negative-unate | when gated == 1 |
| MUX | positive-unate with clock1 | when select == 0 |
| MUX | positive-unate with clock2 | when select == 1 |
Therefore, for all gated clocks on the clock network, users need to specify their monotonicity so that STA can perform correct analysis.
Clock gating check (clock gating check)
Through the above description, we can see the importance of the always network for static timing analysis, so the inspection of the gated clock on the propagation path of the clock network is particularly important. Similarly, based on the clock gating structure, for the active high and active low gating clocks, use the STA tool. The corresponding clock gating check can be automatically inferred (infer), and users can understand that the clock gating structure here is covered by STA. Therefore, users need to understand the principle of STA's automatic deduction, so as to ensure that their clock paths are covered by STAs.
definition
The basic criteria for the tool to judge the gated clock are as follows
- There must be a combinational logic propagation path from the input clock to the output. Conventional AND or NOT, or conventional latch based clock gating structure (see the figure below), but the frequency division structure of register is not a clock gating.
- The input port must contain the clock, but the input-to-output propagation must contain the data path (gated signal).
Example 1: The input of the combinational logic is clock, STA will automatically propagate the clock to the output, so that the output will see four clocks, such a structure cannot be judged as a clock gating structure, when the user needs to use it, when When clock1 is valid, clock2/3/4 needs to maintain a constant 1, otherwise the output clock will be confused
Example 2: The input is all clocks, but the user creates a gen-clock in the output using the following command
create_generated_clock -name clock1_gen_clk -divide_by 1 \
-source clock1 [get_pins U1/Z]
Since this AND is only propagated by clock1, STA will automatically infer that this is a clock gating structure, the gating check from clock1 to clock2, and the clock2 signal is a gating signal (enable)
Example 3: A complex gating clock cannot be automatically deduced.
The UMUX0 here satisfies the clock gating structure,
but since the MUX structure is a non-monotonic propagation (none-unate), such a clock gating structure cannot be automatically deduced (auto-infer ), so there are risks in the clock propagation path, so the tool will give the following prompts. Needs further user action
challenge
The gated clock is inserted with OR logic in the propagation path of the clock, and the designer achieves the operation of the clock through certain logic control:
- Clock frequency division: use low-frequency gating signal and high-frequency clock and do AND operation:
clock_slow = clock_fast * slow_enable - Clock switching: using semi-static signals (nearly always off control):
block_clock = sys_clock * block_enable - Clock selection: Use semi-static signals (close to mode control):
clock_out =（sel==1'b0）？func_clock : scan_clock
or use the latch/reg structure to design an anti-shake clock switching, but no matter how complicated the generation of the gating signal is, as long as it conforms to the structure of moderate gating, the final The point of clock gating check will not change. It is just a good clock generation (clock-gen) design, which can be more friendly to STA, promote project quality and accelerate project convergence. This is also an experienced design engineer. basic practice.
The clock is a periodic change. If a combinational logic operation is performed with a gating logic, the problem of clock waveform propagation (clock crop or clock swallow) usually occurs:
The enable signal that appears at different stages will cause the waveform of the clock to be distorted
| Phenomenon | Influence |
|---|---|
| frequency slows down | Has an impact on neg-latch timing |
| frequency becomes faster | Impact on setup |
| widened pulse width | Has an impact on neg-latch timing |
| pulse width narrowing | Has an impact on min-width-pulse |
Note: In the STA timing report, the user will not see the impact of the above problems, but in the actual chip, this impact is real . Therefore, the logic of clock-gating must be covered by clock-gating-check, and it needs to be repaired carefully. For clock-gating points that cannot be automatically inferred by the tool, users need to focus on and give solutions, otherwise in There will be timing problems in the final chip that are completely inconsistent with STA (cannot be located by STA).
To Be continued… (To Be continued …)
After this treatment, the port mismatch of LVS std-cell is perfectly solved,
learn v2lvs well, and no longer need perl to patch source netlist~~~~
[Knock on the blackboard to draw key points]
Understanding clock-gating-check is as important as understanding clock-gating, and any action on the clock tree requires extra care
References
J. Bhasker and Rakesh ChadhaStatic Timing Analysis for Nanometer Designs
Synopsys PrimeTime® User Guide