Core Driver's "Daily Question" will update an IC interview written test question every day (some of the questions have been adopted by many companies for reference), you are smart, come and challenge it!
Today is question 43
The low-power design strategy has been introduced systematically in the previous real question. In this question, we will strengthen the use of CG (clock gating) cells by modifying the circuit.
That's it for today's question, let's start solving it
Post the answer!
As stated in the commentary:
The circuit in this question is often used when writing code, and the Verilog code corresponding to the circuit diagram is also given in the manuscript. How to reduce power consumption, the most effective way is to stop the clock besides power off. This is the value of the existence of the CG cell. The existence of the clock is controlled by EN. If the flip rate of EN is very low, the register basically only has static power consumption. up. The insertion of CG cells is done automatically by tools during the circuit synthesis stage.
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