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1. Why do you need clock gating?
1- Static Power Consumption
Power consumption in a chip can be broadly defined as dynamic power consumption and static power consumption.
Static power consumption usually includes leakage power consumption generated by the chip in the state of not flipping (power consumption caused by not closing tightly) , power consumption caused by substrate current , power consumption caused by current effect caused by thermal electron effect, etc., and some components .
Usually, static power consumption is difficult to make some optimizations in the front-end design stage (power-off processing can be done) . It is generally based on the ME/BE process or process improvement to achieve better results.
The static power consumption is as follows:
2- Dynamic Power Consumption
The source of dynamic power consumption usually consists of two parts,
1 - Part 1
- The first part, the largest part of the power consumption in the chip is the power consumption caused by the charging and discharging of the cell , as shown in the figure below, taking the Inverter (transformation) circuit as an example, it is composed of a PMOS and an NMOS, and the output can be It is equivalent to think that there is a capacitance to ground,
Every time IN is from 0 to 1, the PMOS will change from on state to off state. On the contrary, the NMOS will change from the off state to the on state. This causes the capacitor to discharge from the NMOS to ground.
On the contrary, when IN changes from 1 to 0, it will cause the capacitor to be charged through the PMOS , and this charging and discharging process will consume a large part of the electric energy, thereby generating power consumption.
the second part
The other part of the dynamic power consumption is the power consumption generated when the PMOS and NMOS are turned on at the same time during the cell flipping process, which is also called internal power . NMOS is in the conduction state at the same time , and a DC path from VDD to GND will appear at this time. Although this process is very short, the resistance in the circuit is very small during this process, so the current in the entire path is very large. .
But despite this, compared with the dynamic power consumption mentioned above, the proportion is still relatively small.
summary
From the above analysis, it can be seen that the dynamic power consumption is all caused by cell flipping . In the chip, the path with the highest flipping frequency is the clock path. And what to do on the clock path is CTS processing (clock tree), which will cause a lot of CK-BUF or CK_INV on the entire clock path.
The flipping of each cycle of the clock will drive the flipping of all cells on the entire path . According to statistics, in a chip, the power consumption on the clock path can account for 40% or more of the power consumption of the entire chip. Therefore, dynamically shutting down the clock path can greatly save power consumption . This technique of turning off the clock is called clock gating.
2. How to do clock gating (based on CELL)?
As shown in the figure above, data_out can be considered as a DFF after being implemented. The data of this DFF is not valid for every clock cycle, only when data_en==1. DFF will be rewritten only once on the rising edge of clock. On the rising edge of other clock cycles, the DFF data will not actually be overwritten again. This provides us with an idea. In fact, the inversion of the clock is only meaningful if data_en is 1, and other cycles are invalid inversions.
**How to save the power consumption caused by these invalid clock flips? **In fact, we only need to be able to achieve the following clock waveform.
With this idea, it is easy for us to find a solution. Seeing the waveform, we can easily think that the clock can be AND/ORed in the way of AND-GATE or OR-GATE, so that we can achieve the effect we want.
Through AND-GATE or OR-GATE to do calculations with the original CLK, after **converting the original CLK to CLK_G,** you get a waveform that the clock will flip only when EN is valid. The conversion process of this form is the most basic form of clock gating.
Although the circuit of this basic form of clock gating is simple, some problems must be considered and avoided in the process of actual implementation and use.
Based on the clock gating in the form of AND-GATE, due to the function of AND, the signal when the clock is at a high level will be passed. This will introduce a problem, we must ensure that the EN signal is stable during the high level of the clock, and there must be no glitch, otherwise the obtained clock -CLK_G will produce a glitch (glitch).
So how to ensure that the EN signal is stable during the high level of the clock? It is easy to think that the source of the EN signal cannot be a register triggered by a rising edge. If the EN signal is generated from the register triggered by the rising edge, then after the combinational logic, it is easy to generate the following glitch during the high level of the clock :
To solve this problem, trigger the source of EN on the falling edge of the register , * *In this way, the EN signal has half a cycle time before the rising edge of the first clock, which can stabilize the EN signal, **that is, the purpose of making the EN signal stable before the rising edge of the clock is achieved.
And based on the clock gating circuit in the form of an AND gate, the ME/BE tool must be able to check and constrain this point when checking timing.
If the EN signal can be stable before the rising edge of the clock, that is, the EN signal will not have a glitch during the high level of the clock, this can ensure that the final generated clock is stable without glitch. (to be understood)
Similarly, clock gating based on OR-gate also requires similar considerations. Only after analysis, it will be found that the register generated by EN needs to use the register triggered by the rising edge.
Finally, we can conclude: if clock gating is to be done based on ANG-GATE, EN needs to generate logic to trigger DFF triggered by falling edge; if clock gating is to be based on OR-GATE, EN needs to generate logic to trigger DFF triggered by rising edge.
In the process of analysis above, we also mentioned that based on this basic CELL method of clock gating, it only takes half a cycle for the EN signal to stabilize the operation.
3. How to do clock gating (high frequency based on ICG)?
If the clock frequency of gating is particularly high, there may be a timing problem that is difficult to converge.
To solve the above problem, the stabilization time of the EN signal can be extended . In other words, it is necessary to "borrow" half a clock cycle to stabilize the EN signal . This can use another basic CELL—LATCH (latch) , which can be used to borrow time in the circuit, which is called timing borrow .
As mentioned in the previous article about latch, in digital circuits, it is very undesirable to have a latch. The main point is its timing borrow property, which will increase the difficulty when doing timing.
But there are two places where the latch circuit is often used, one is the implementation of clock gating to be mentioned here.
The other is to solve the hold timing problem in DFT.
latch + AND gating circuit
A first-level clock low-active latch is added before the original AND to form a circuit structure as shown in the figure, and its timing diagram is shown below in the figure.
Since the added LATCH is active at low level, even if the EN signal is unstable and glitch exists during the period of CLK at high level, it will not be transmitted through LATCH. The AND circuit added after LATCH ensures that the EN glitch transmitted to LATCH during the low level period is blocked.
This ensures that the EN signal can be toggled freely within the entire CLK cycle. The special attribute of LATCH is that the EN signal can be latched into the latch during the half cycle period when the CLK is low. As long as the EN signal is stable before the next rising edge of CLK comes (guaranteeing the setup/hold time of the latch), it can Latch in the correct EN signal.
Based on this structural clock gating circuit, it can well solve the problem that the EN signal has only half cycle stabilization time.
latch + OR gating circuit
Clock gating circuit form based on LATCH+OR. As shown in Figure 2, the difference between it and the AND form is that the previous LATCH should be replaced by clock high-active, and the effective level of the EN signal will determine whether the inverter CELL exists in the figure, which can be deduced by yourself. I won't go into details.
The clock gating circuit based on this structure can also obtain a CLK cycle time for the EN signal stability.
If you want the LATCH+AND circuit to provide an entire cycle of computing time for the EN signal, then the source register of the EN signal must be triggered by rising-edge; similarly, if you want the LATCH+OR circuit to provide an entire cycle for the EN signal The stabilization time, then the source register of the EN signal is required to be triggered by falling-edge.
STM32 clock
With the increasing shortage of energy and the warming of the earth, the power consumption requirements of electronic products are becoming more and more important. How to reduce the power consumption of electronic products is a problem that every electronic engineer must think about.
For semiconductor products, the power consumption of a digital circuit consists of two parts. One is static power consumption, which is usually expressed as the leakage current of electronic circuits. The control of this part of power consumption mainly depends on the production process and materials used; the other is static power consumption. It is the dynamic working current, and there are many factors that affect this part of the power consumption, such as the way of circuit design, the complexity of the circuit, and the clock frequency during operation.
The clock gating technology discussed in this article is a very simple and effective power consumption control method. Its basic principle is to save current consumption by turning off functions and its clocks that are not used temporarily on the chip.
This clock gating technology is used in STM32. Please see the following figure for the clock distribution diagram of STM32:
The AND gates marked in orange in the figure are used to control the clocks of different modules. Users can turn on or off the clocks of corresponding modules through appropriate register bits in the program to reduce power consumption.
（http://news.eeworld.com.cn/mcu/2015/0414/article_19372.html）