Distinguishing processor architecture instruction set microprocessor architecture
0 prerequisite knowledge
Digital system requires three main components:
- Combinational logic function calculated bit operation (ALU)
- Stored bit memory elements (registers)
- A control clock signal of the memory element update
instruction
An instruction processor completes the process
Instruction fetch, instruction decode and execute instructions
- Fetch (FETCH)
value phase instruction bytes read from memory into the instruction memory (CPU) is, the address of the program counter (PC) value.
It calculates the current instruction in a sequential manner the next instruction address (PC value plus the length of the instruction has been removed) - Decoding (decode)
the ALU read up to two operands from the register file (general-purpose register set). (I.e., a read up the contents of two registers) - Execution (Execute)
in the execution stage according to the type of instruction, the arithmetic / logic unit (ALU) for different purposes. Other commands, it will be calculated as a adder increase or decrease the stack pointer, or calculating an effective address, or simply adding 0, one input to the output.
Condition code register (CC) bits there are three conditions. ALU responsible for calculating the new value of the condition code. When executing a jump instruction, the branch will be calculated and the signal cnd jump condition code type.
Clock cycle
machine cycle
instruction cycle
program
When we write programs can actually program code is divided into two parts,
part of a program written after the completion of the modification is no longer needed them (that is, logical code section) instruction
after another part of the programming is completed with its content will run the program and the changing part (that is, the definition of variables). Data
Harvard structure and von Neumann architecture is the difference for the storage of this two-part code.
Note
Processor architecture and instruction set of the processorThere is no particular correspondence between。
X86 instruction set may be employed with the microstructure of MIPS, MIPS instruction set may be used on the microstructure x86 processors.
Instruction set architecture of the processor does not determine
1 Instruction Set Architecture (Instruction Set Architecture, ISA)
A processor supports byte-level instructions and coded instructions called its instruction set architecture ISA system. Sets out how the processor to identify these assembly instructions, as well as how to interact with the upper layers.
The instruction set in which some, 0000 on behalf of add, so the same binary string is interpreted differently in different instruction sets.
CISC (complex instruction set)
(Complex Instruction Set Computer)】
intel 的x86，
Reduced instruction set (RISC)
Reduced Instruction Set Computer
using RISC instruction in the high-end server CPU mainly Compaq (Compaq, that the new HP) the company's Alpha, HP's PA-RISC, IBM's PowerPC, MIPS's MIPS and SUN's Sparc .
the difference
1. Instruction: RISC designers to focus on those frequently used instructions, try to make them simple and efficient. To commonly used functions, often done by a combination of commands. Therefore, when implementing special functions on RISC-based computers, it may be less efficient. But it could be improved and make up for the use of pipelining and superscalar techniques. While CISC instruction set computer rich, with special instructions to perform specific functions. Therefore, the higher the efficiency of special tasks.
2. Memory operations: RISC memory has operating limits, control can be simplified; and the memory operation instruction multiple CISC computer, direct manipulation.
3. Program: CISC assembly language program generally requires more memory, the special function program implementing complex and difficult to design; and RISC assembly language programming relatively simple, scientific computing program and relatively easy to design a complicated operation, high efficiency.
4. Interrupt: RISC computer in the appropriate place in response to execution of an instruction may be interrupted, but the time is short compared to CISC instructions for execution, the interrupt timely response; while CISC computer is an instruction executed after the interrupt response.
5.CPU: RISC CPU with fewer unit circuit, and thus small size, low power consumption; CISCCPU the circuit unit contains a wealth, so powerful, large-area, high power consumption.
6. design cycle: RISC microprocessor architecture simple and compact layout, a short design cycle, and easy to use the latest technology; complex CISC microprocessor architecture, design cycle length.
7. User: RISC microprocessor architecture is simple, regular instruction, performance, easy to grasp, easy to use; complex CISC microprocessor architecture, powerful, easy to implement special features.
8. Applications: Due to determine CISC instruction set associated with a particular field of application, it is more suitable for CISC computer dedicated machine; the RISC computer is more suitable for general-purpose machine.
2 processor architecture (CPU architecture)
CPU architecture, processor architecture, the central processor architecture. . . whatever
Von Neumann architecture
Also known as the Princeton Architecture (Princetionarchitecture). It isWe are talking about X86 architecture
Structural features
The core is:Mixed data and instructions, unified addressing. Program instructions and data memory of a memory structure combined.
The instruction fetch and operand fetch are on the same bus, by way of time division multiplexing. Share the same bus structure, so that the transport stream to be limiting of computer performance bottlenecks, which influences the speed of data processing. FIG
Since the program instructions stored address and the stored data addressed to a different location in the same physical memory, and thereforeSame width program instructions and data.
Distinguish which is the command and data which are substantially the following methods:
1, the instruction register and to distinguish between data and instructions cycle. For example: CS segment (codesegment code segment) and a segment DS (datasegment data segment), the former is considered to CPU instructions are stored, which data are stored in that CPU;
2, to distinguish between instructions and data over different time periods, extracted in the stage is the instruction fetch, execution stage data is extracted.
Advantages and disadvantages
Simple structure, easy to implement, low cost, low efficiency
eg
Intel's X86 microprocessor
Von Neumann architecture is mainly based on a different computer buyers use the computer's way - a variety of entertainment users, various types of users such as professional development, and installation of a wide range of software, upgrades frequently deal with a variety of software running simultaneously the priority is vague, Intel chip does not have the mechanisms and priority lines of each program thoroughly intelligent distribution, allocation priorities and pipeline machinery but easy to make the user inconvenience.
arm7 series CPU has a lot of money, which is not part of the CPU internal cache, such as arm7TDMI, is pure von Neumann architecture, and other internal data cache and instruction cache separate cpu use a Harvard architecture.
Harvard architecture
Structural features
It is separate instruction and data area. Independent addressing, even if the same address, the data is not the same. and soInstructions and data may have different data widths, As program instructions Microchip's PIC16 chip is 14 bits wide but the data is 8 bits wide.
Harvard architecture, since the instruction fetch and data access, respectively, viaDifferent storage space and different bus, So that each instruction can beOverlapping executionSuch that it overcomes the bottleneck of data streaming, to improve the processing speed. Harvard architecture emphasizes the speed and flexibility of the overall system configuration of the communication and processor. The purpose is to reduce the memory access bottleneck when the program runs.
The most common example of a convolution operation, an instruction fetch two operands simultaneously, while the pipeline processing, as well as a fetch operation, if the program and data through a bus access, and access fetch conflict will occur, the efficiency of this cycle of large amount of computation is very unfavorable. Harvard architecture can basically solve the fetch and take the number of conflicts.
Advantages and disadvantages
Complex but high structural efficiency, high processing requirements of the connected peripheral devices, peripheral memory is not suitable for extended
eg
Currently the use of central processors and microcontrollers Harvard architecture, there are many, DSP and ARM represented.
High performance reflects less Harvard agencies in the program and the type of pattern that runs on the microcontroller, DSP chip platform, because the individual electronic entertainment products the software upgrade is relatively small, the application can be compiled as a kernel, the most efficient use of pipeline technology, maximum efficiency.
In addition to Microchip's PIC family of chips, as well as Motorola's MC68 series, Zilog's Z8 series, ATMEL's AVR series and ARM's ARM9, ARM10 and ARM11.
Modified Harvard
Although the modified Harvard architecture also uses two different memories: a program memory and data memory, but the two merged memory address bus, data bus also merged, i.e. the original Harvard architecture requires four different bus, the improved requires two buses.
Structural features
Two separate memory modules, storing instructions and data, respectively, each memory block are not allowed to coexist instructions and data, in order to achieve parallel processing;
Having a separate address bus and a separate data bus, using a common address bus to access two memory modules (memory modules and program data storage module), were used to complete the common data bus or data storage module storing a program and a CPU module data transmission between the;
two time-shared bus by the program memory and data memory.
eg
Today's processors, relying on the existence CACHE has been very good to unify them up. Today's processors, although the external bus is seen Neumann architecture, but because of internal CACHE, so in fact the internal point of view has a similar structure of the modified Harvard.
Processor 3 microstructure (micro-architecture)
After the processor recognizes these instructions, it is what the microstructure of how to perform these instructions. For example, you can design the ALU three adders, while performing three addition instruction in a cycle which can also be designed a two multiplications + the ALU adder, an adder + perform two multiply instructions simultaneously in one cycle inside.
4 based on the company's architecture
arm architecture
arm company
x86
MIPS
PowerPC
