Instruction format
ARM basic format
<opcode>{<cond>}{S}{.W|.N}<Rd>,<Rn>{,<operand2>}
opecode: instruction mnemonic
cond: execution condition
| Mnemonic |
Mark |
meaning |
| EQ |
Z = 1 |
equal |
| BORN |
Z = 0 |
not equal |
| CS/HS |
C=1 |
Unsigned number greater than or equal |
| CC / LO |
C=0 |
Unsigned number less than |
| MY |
N=1 |
negative number |
| PL |
N=0 |
Positive or 0 |
| VS |
V = 1 |
overflow |
| YOU |
V = 0 |
No overflow |
| HI |
C=1，Z=0 |
Unsigned number is greater than |
| LS |
C=0，Z=1 |
Unsigned number less than or equal |
| GIVE |
N = V |
Greater than or equal to Signed |
| LT |
N! = V |
Signed number less than |
| GT |
Z = 0, N = V |
Signed number greater than |
| THE |
Z = 1, N! = V |
Signed number less than or equal |
| AL |
any |
Performed unconditionally (instruction default condition) |
S: instructions affect the CPSR
.W and .N: width specifier, the default 16-bit, 32-bit specifier used .W. ARM and Thumb can be used
1. Jump instruction, 4
1. Jump B: B {cond} label
2. BL with link (similar to single step into) the current address of the next instruction stored in the instruction register R14, used to call the subroutine: BL {cond} label
3. BX with jump state switching (switching between the ARM and Thumb) Rm processor determines the bit [0] is 1, then the CPSR flag T is set, switch to Thumb, conversely switched ARM: RX {cond} Rm
4. And link-state switching with BLX jump: BLX {cond} Rm
2. Memory access instructions:
LDR: a memory register ←
Format: LDR {type} {cond} Rd, label LDRD {cond} Rd, Rd2, label
Type Value:
B: unsigned byte (0 loading extend to 32 bits)
SB: Signed byte (32-bit sign-extended to loading)
H: Unsigned nibble (0 loading extend to 32 bits)
SH: Signed nibble (sign-extended to 32-bit loading)
Rd: Load Register
Label: memory address read
LDRD: once data is loaded double word
STR: memory register →
STR{type}{cond} Rd,label
STRD{cond} Rd,Rd2,label
Type in the SB and HS for STR invalid
LDM plurality of memory cells can be specified: memory register ←
LDM{addr_mode}{cond} Rn{!} reglist
addr_mode:
IA: Increase After, the base register after execution of the instruction is increased, the default
IB: Increase Before, the base register before the instruction to increase (ARM only)
DA: Decrease After, the base register after execution of the instruction to reduce (ARM only)
DB: Decrease Before, the base register before the instruction to reduce the
FD: full descending stack, Stack grows toward a lower address, the valid data stack pointer points to the last item of the stack
FA: full incremental stack, the stack grows toward greater addresses, under the stack pointer to put in a blank address
ED: Empty decrements the stack, the stack growth to address low
EA: hole increments stack, the stack grows toward greater addresses
Rn: base address register to store the initial address
! : Optional suffix, will have the final address is written back into Rn register
reglist: register list store data, a plurality of consecutive registers available "-" link, with discontinuous "," separator
STM: register list memory data →
STM{addr_mode}{cond} Rn{!} reglist
PUSH: Push registers onto full descending stack
PUSH{cond} reglist
POP: pop the register information from a full descending stack
POP {cond} reglist
SWP: memory register ← →
SWP{B}{cond} Rd,Rm,[Rn]
B: Alternatively bytes, then the switch with a B byte 32-bit word or exchanged
cond: execution condition
Rd: data loaded from memory register
Rm: writing data to the memory register
Rn: a memory address of data to be exchanged. Rn must be different Rd and Rm
Eg: SWP R1, R1, [R0] R1 and R0 exchange
SWPB R1, R2, [R0] R0 is a clear high byte to R1 0, R2 to memory
3. Data processing instructions: data transfer, arithmetic operations, logic operations, comparison 4 classes.
Data processing instruction is the operation of data between a register, deciding whether to use the S suffix can affect the status flag.
Comparison instruction, need not directly affect the status flag S suffix
MOV: the register contents or an immediate transfer to the 8-bit target register
MOV{cond} {S} Rd，operand2
MVN: the register contents or an immediate 8-bit bitwise moved to a destination
MVN{cond}{S} Rd，operand2
ADD
ADD{cond}{S} Rd，Rn，operand2
ADC: Carry the operand2 registers Rn value is added, plus the value of the condition flag C CPSR register to save the register Rn
ADC{cond}{S} Rd，Rn，operand2
SUB：Rn-operand2
SUB{cond}{S} Rd，Rn，operand2
RSB：operand2-Rn
RSB{cond}{S} Rd，Rn，operand2
SBC: condition flag value C Rn-operand2-CPSR register
SBC{cond}{S} Rd，Rn，operand2
RSC: condition flag value C operand2-Rn-CPSR register
RSC{cond}{S} Rd，Rn，operand2
MUL：Rd=Rm*Rn
MUL{cond}{S} Rd，Rm，Rn
MLS：Rd=Ra-Rm*Rn
MLS{cond}{S} Rd，Rm，Rn，Ra
UMULL: Rm * Rn value into high RdHi = 32, RdLo = Low 32
UMULL{cond}{S} RdLo，RdHi，Rm，Rn
SMULL: Rm * Rn value as an unsigned number into a high RdHi = 32, RdLo = Low 32
SMULL{cond}{S} RdLo，RdHi，Rm，Rn
UMLAL: Rm * Rn value as an unsigned number into a 32-bit RdHi = high, low RdLo = 32, 64 then results in that the addition and RdLo RdHi
UMLAL{cond}{S} RdLo，RdHi，Rm，Rn
SMLAL: Rm * Rn value as a signed number into RdHi 32 = high, low RdLo = 32, 64 then results in that the sum and RdLo RdHi,
SMLAL{cond}{S} RdLo，RdHi，Rm，Rn
SMLAD: Rd = Rm * Rn (all low nibble) + Rm * Rn (both nibble) + Ra
SMLAD{cond}{S} Rd，Rm，Rn，Ra
SMLSD: Rd = Rm * Rn (all low nibble) -Rm * Rn (both nibble) + Ra
SMLSD{cond}{S} Rd，Rm，Rn，Ra
SDIV: signed divide
SDIV{cond} Rd，Rm，Rn
UDIV: unsigned division
UDIV{cond} Rd，Rm，Rn
ASR: arithmetic shift right
ASR{cond}{S} Rd，Rm，operand2
AND
AND{cond}{S} Rd，Rn，operand2
ORR
ORR{cond}{S} Rd，Rn，operand2
EOR
EOR{cond}{S} Rd，Rn，operand2
BIC: Bit Clear instruction, the operand2 negated, and the Rn value and save the operation results to Rd
BIC {cond}{S} Rd，Rn，operand2
LSL: Logical Shift Left
LSL{cond}{S} Rd，Rm，operand2
LSR: Logical Shift Right
LSR{cond}{S} Rd，Rm，operand2
ROR: Rotate Right, bits shifted back to the left
ROR{cond}{S} Rd，Rm，operand2
RRX: rotate right with extend, Rm rotate right one, the value of the most significant bit is filled with a flag register and stores the result Rd
RRX{cond}{S} Rd，Rm
CMP: Rn-operand2, flags are set according to the result
CMP{cond} Rn，operand2
CMN: Rn + operand2, flags are set according to the result
CMN{cond} Rn，operand2
TST: bit test instruction, Rn and operand2 operation, set flag bit according to the result
TST{cond} Rn，operand2
TEQ: bit test instruction, Rn XOR operation and operand2, flags are set according to the result
TEQ{cond} Rn，operand2
4. Other instructions:
SWI: Software interrupt instruction
SWI{cond}，immed_24
Android system, the system call to the interrupt number 0, R7 system call number storage register, R0 ~ R3
The delivery system call before four parameters, greater than four parameters call stack
NOP: blank instruction
MRS: read status register instruction
MRS Rd, psr psr argument can be CPSR or SPSR
Write Status Register instruction MSR
MSR Rd，psr_fields,operand2
field specify delivery area (field must represent letters in lower case):
c: Control byte mask field (psr [7 ... 0])
x: extension field mask byte (psr [15 ... 8])
s: status byte mask field (psr [23 ... 16])
f: flag byte mask field (psr [31 ... 24])