ARM was founded in 1991 in Cambridge, England, in the years after the establishment, ARM mediocre performance, engineers have panic, fear of unemployment at any time. In this case, ARM decided to change their product strategies - they no longer produce chips instead to authorize a way to transfer chip designs to other companies, namely "Partnership" open mode.
I did not expect this pattern, creating a new era belong to the ARM.
ARM taken is IP (Intellectual Property, intellectual property) licensing business model, receive a one-time license fee and royalties technical commission.
Specifically, ARM has three License: processor, POP and architecture license.
Processor licensing refers to authorized partners use ARM-designed processor, the other party can not change the original design, but you can adjust the frequency of the product, the power consumption according to their needs and so on.
POP (processor optimization pack, processor optimization package) is authorized processor licensing of advanced form of the ARM processor optimized for sale to authorized partners, to facilitate the design in a particular process to produce guaranteed performance processor.
ARM architecture license is authorized partners will use their own architecture, its easy to design according to their needs processor (such as Qualcomm's Krait architecture later and Apple's Swift architecture, that is, after obtaining the authorization of the ARM design is completed). So, licensing fees and royalties became the main source of income of ARM. In addition, revenue is software tools and technical support services.
First, the application field of ARM microprocessor and features
ARM processor market coverage the most, the development trend of broad-based 32-bit ARM microprocessor technology, the market share has now reached 80%. The vast majority of IC manufacturers have launched their own ARM architecture chips. Our ZTEIC, Datang Telecom, Huawei Hass, SMIC and Shanghai Hua Hong, as well as some foreign companies such as Texas Instruments, STMicroelectronics, Philips, Intel, Samsung and so launched their own design based on ARM core processor.
Industrial control: RISC architecture as 32, based on ARM core microcontroller chip not only occupy most of the market share in the high-end microcontroller market, but also gradually extended to low-end micro-controller applications, ARM microcontrollers low-power, cost-effective, it challenges the traditional 8/16-bit microcontrollers.
Wireless communications: there are more than 85% of wireless communications devices using ARM technology, ARM for its high performance and low cost position in the field of increasingly consolidated.
Network equipment: With the promotion of broadband technology, ADSL chip using ARM technology is gradually gain a competitive advantage. In addition, ARM carried out on voice and video processing has been optimized, and received widespread support, but also poses a challenge for applications of DSP.
Consumer electronics: ARM technology is widely used in popular digital audio players, digital set-top boxes and game machines.
Imaging and security products: the now popular digital cameras and printers in the vast majority of ARM technology. Phone 32 SIM smart card also uses ARM technology.
ARM processor features:
1, small size, low power consumption, low cost, high performance;
2, support the Thumb (16-bit) / ARM (32-bit) dual instruction set, can be well compatible with the 8/16-bit device;
3, extensive use of registers, instruction execution faster;
4, most data operations are completed in the register;
5, flexible and simple addressing modes, high efficiency;
6, the instruction length is fixed;
Two, ARM several important concepts related
1. Von Neumann architecture
Von Neumann architecture features:
A, data and instructions are stored in the same storage area, the data fetch instruction fetch using the same data bus.
B, is used by most computers early.
C, ARM7-- von Neumann architecture is simple, but slower. You can not take simultaneously fetch data.
2. Harvard system
Structural features:
A, a separate program and data memory.
B, provides a greater memory bandwidth, each have their own bus.
C, suitable for digital signal processing.
D, most of the DSP are Harvard architecture.
E, ARM9 Harvard structure, and fetch the fetch in the same cycle, the speed increase, modified Harvard architecture is divided into three memory areas: program, data, programs and data sharing.
Characteristics of a complex instruction set 3.CISC
A, having a large number of instructions and addressing modes
B, 8/2 principles: only 80% of the program instruction 20%
C, most applications use only a small amount of instruction will be able to run.
D, CISC CPU contains a wealth unit circuit, and thus powerful, large-area, high power consumption.
4.RISC Reduced Instruction Set Features
A, in the channel only contains the most useful instruction, only provides simple operation.
B, the channel data to ensure rapid execution of each instruction.
C, Load-store architecture - a processor for processing data only register, load-store instruction to complete the transmission of data between the register and the external memory.
D, so that the CPU hardware architecture design becomes simpler, RISC CPU unit circuit comprising less, and thus a small area and low power consumption.
The main difference between CISC and 5.RISC
A, of the registers
RISC instruction set: have more general purpose registers, each of which can store data and address registers all data operations to provide quick access to the storage.
CISC instruction set: a plurality of special purpose registers used for specific purposes.
B, LOAD -STORE structure
RISC architecture: Cpu only process data register, using a separate, dedicated LOAD -STORE instructions to complete the data transfer between registers and external memory. (Consuming memory access, process and store separately, can be repeatedly used data stored in the register, while avoiding multiple access external memory).
CISC structure: it can directly process the data in the memory.
Three, ARM storage format
ARM is a 8-bit memory cells for storing data (one byte), a memory address assigned to each memory cell.
ARM memory regarded as a linear combination of bytes starting at address zero. As a 32-bit microprocessor, ARM architecture supports a maximum address space of 4GB (232 bytes). Three-byte from zero byte to place the first data word stored in the word data from the fourth byte to the seventh byte stored in second place, in order of priority. 32-bit word data to address unit using four 16-bit data to use two half address cells. Thus, there is the problem the order of the data word or a halfword stored. ARM architecture stores word data in two ways, known as big endian and little endian format.
Big-endian format (big-endian): High byte of word data stored in the lowest address and the low byte of the data word is stored in high address.
Little endian (low-endian): In contrast to the big-endian storage format. Low address stored in the low byte of the data word, the address is stored in the high byte of the high word of data. The default setting is little endian format.
Do you really know the size of the CPU end model?
Four, Thumb technology
Development of ARM RISC architectures have been provided in the low power consumption, small size, high performance solutions. In order to solve the problem of the length of the code, ARM architecture has increased the T variant, developed a new command system, which is the Thumb instruction set, which is a major feature of ARM technology.
Thumb is an extension of the ARM architecture. It has the standard 32-bit ARM instruction set 36 out to the instruction format can be re-compiled in 16-bit opcode. This will bring high code density.
Thumb-ARM architecture processor state can be easily switched to the operating state of the Thumb instruction set is a state in which the 16-bit Thumb instruction set.
ARM instruction set and instruction set compared .Thumb following limitations:
1, the same operation is completed, Thumb instructions typically require more instructions, so the run-time system demanding applications more suitable ARM instruction set;
2, Thumb instruction set does not contain some of the instructions required during exception handling, so when abort, or ARM instructions required, this limitation determines the Thumb instructions and the ARM instructions used in conjunction with the need.