Computer hardware knowledge] CPU architecture and instruction set
https://blog.csdn.net/antony1776/article/details/83743856
Four CPU architectures: ARM, X86, MIPS, PowerPC
ARM low-power, wireless LAN, 3G, mobile terminals, handsets, wired network communication device is widely used;
the MIPS: CISCO large number of companies are in the high-end routers;
the PowerPC: a wide range of industrial control communications and applications processors, Huawei, ZTE's equipment,
the central processor architectures:
Von Neumann: a program instruction memory and data memory structures merged together;
Haversian structure: stored separately;
Instruction Set:
RISC: With fewer instructions, the instruction execution cycle single, larger object code; the ARM, the MIPS, the PowerPC
CISC: complex instruction, a long instruction cycle, multi-object code; the X86,
The reasons for the low-power ARM when it comes to head is out of order less able than X86. In other words, the user when using the computer, his operation is random, unpredictable, causing instruction can not predict. In order to enhance the processing power of X86 in this case, to strengthen the out of order instruction execution also enhances the multi-threading capability of a single core. The downside to this is that not very effective closure and restoration processor sub-module, because once turned off, recovery is very slow. To maintain high performance, you have to make most of the module remains open, and the clock remains high-speed switching. Direct consequence of the high power consumption. The ARM RISC instruction optimization of strength in order to determine performed, and instead rely on a multi-core multithreading performed monocytes, remains closed so easily submodule and clock signals, obviously more power.
Memory: ROM (read-only), Flash (NOR, NAND), RAM (Random Access Memory)
RAM: Static RAM (SRAM); Dynamic the RAM (a DRAM);
a DRAM stores a charge in the form of data stored in the capacitor, the capacitor will cause charge loss due to leakage, periodically needs to be refreshed;
the SRAM: a long supply time will remain value;
serial bus:
the USB:
Ethernet interfaces:
By the MAC (Ethernet media access controller) and PHY (physical interface transceiver), respectively in the data link layer and the physical layer;
the CPU directly interact with the MAC, the Ethernet hardware interfaces are configured, CPU-> MAC ----> PHY -----> Ethernet isolation transformer ----> RJ45 connectors;
schematic analysis:
FIG principle reading board obtained various hardware resources memories, peripherals used, including the memory and peripheral chip select control chip used, interrupts, and DMA resources;
hardware schematic of the elements: the symbol, the network, description;
hardware timing analysis: circuit board debugging tasks, master timing analysis method would have more necessary;
instruments used: multimeters, oscilloscopes,
register:
Is part of the central processor is limited storage capacity high-speed storage means, they can be used for temporarily storing instructions, data, and address. 32 CPU
-8086 registers: general purpose registers, instruction pointer, flag registers, segment registers.
working principle:
When the cpu processed data in the memory, the data tends to get into the first internal register, and then do the processing.
Order execution techniques: causing the CPU running at full capacity and the internal circuit corresponding increase in speed of the CPU to run the program.
Use: 1, the internal data registers perform arithmetic and logic, 2, stored in the address register may be used to point to a location in memory, addressing, 3) read and write data to the computer peripheral equipment.
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