1.1 Electronic

The basic elements of electronic parts; the device is often composed of several elements, sometimes also referred to larger elements.

Elements include resistors, capacitors, inductors; means more diverse, with a bipolar transistor, field effect transistors, thyristors, semiconductor as resistors and capacitors.

Element no voltage, and converting the current control action; the device has control of the voltage, current, effect conversion (enlargement, switches, rectifier, detection, modulation and oscillation).

Reference: http://m.elecfans.com/article/589969.html distinguish elements and devices

1.2 Circuit

Analog circuit:

Analog signal processing circuit, such as a alternating voltage of the operational amplifier the amplified output a large AC voltage, the signal processing is continuously changed, as a continuous alternating current sine wave. Analog circuit operational amplifiers, modulation and demodulation circuit, oscillation circuit.

Gates: basic logic operations (with AND gates , OR gates , NOT gates , NAND gates , NOR gates , and NOR gate, XOR gate , etc. Several) unit circuit.

Digital circuits:

A circuit for processing digital signals, the signal processing circuit 0 is not representative of a low level, 0, 1, high, basic gate circuit is composed of the original . Because of its logical arithmetic and logic processing functions, it is also known as a digital logic circuit .

Depending on the characteristics of digital circuit logic functions, it can be divided into two categories:

One is called a combination logic circuit (abbreviated combining circuit), and the other is called the timing logic circuit (referred to as a sequential circuit).

Features in the combining circuit is an output logic function depends only on the input at any time of the time, regardless of the original state of the circuit.

The timing circuit is output at any time depends not only on the time of the input signal, but also on the original state of the circuit, or say, but also on the previous inputs. There trigger counters, registers, etc.

2. The machine language and decoder

Machine language is binary code representing the computer can be implemented, a set of machine instructions;

Machine language and decoder

Command (command register) = operation code (opcode decoder translated to operation of the controller) + address code (supplied to the address register);

Reference: http://m.elecfans.com/article/666558.html a difference between the read packet processors, cores, three chip concepts

Reference: http://www.360doc.com/content/15/0929/22/1564981_502326554.shtml relationship between registers and memory

Reference: https://blog.csdn.net/alianada/article/details/82142379 bottom of the computer what it is?

Reference: https://www.eefocus.com/mcu-dsp/402521/r0 also uses the ARM architecture, the processor Apple stronger than others Why the hell?

Reference: https://www.cnblogs.com/voidobject/p/3975552.html , What is the relationship (rpm) processor architecture, instruction set and assembly language of the three?

Reference: https://blog.csdn.net/p312011150/article/details/79612379 assembly instructions and machine code conversion

Reference: https://blog.csdn.net/dark_tone/article/details/52426886 instruction in the end what is? What is the machine code?

3. The assembly language compiler / instruction set architecture

Assembly: with mnemonics instead of machine instructions of the operation code , the address with a label or a symbol instead of an instruction or operand addresses.

Assembly language and machine language instruction set is one to one, not directly portable among different platforms.

Instruction Set Architecture (ISA): specifies how the processor to identify these assembly instructions, and how to interact with the upper layer, to distinguish between the boundaries of software and hardware. The software portion of the chip. Each instruction corresponds to the instruction set of assembly instructions and fixed with a circuit implementation, the minimum unit of language programming.

As add r1, r2, r3,

In the instruction set XX, 1010 on behalf of add, so this instruction is the instruction code part 1010,

However, the instruction set XX, 0000 on behalf of add, so the same binary string is interpreted differently in different instruction sets.

In a different assembly language it has a different meaning, there may be representative of r1 = r2 + r3, there may be representative of r3 = r2 + r1.

Reference: https://www.cnblogs.com/voidobject/p/3975552.html

Reference: https://blog.csdn.net/qq_34322603/article/details/75276415

Reference: https://blog.csdn.net/yangtalent1206/article/details/6247607?utm_source=jiancool

Assembly language and machine language machine poor portability, because for a particular instruction, different CPU assembly language and machine language can not be universal.

Assembly language and machine language program poorly structured, is not easy modular design also caused portability poor.

Instruction set architecture is a patent, not copyright.

There ARM V1 ~ V8 ARM instruction set architecture, (V8 instruction set refers to the version number, ARM architecture).

Intel instruction set

Intel had x86, SSE, AVX instruction set architecture, AMD has x86, x86-64,3D-Now! Instruction set.

x86 refers to a series based on the Intel 8086 and is backward-compatible instruction set

In 1971, Intel invented a world's first commercial microprocessor -4004, only 45 instructions , executed 50,000 instructions per second, the speed is only 108KHz, even smaller than in 1946, the world's first computer, ENIAC, but have to be much higher degree of integration, integrated transistors 2300, weighs less cup division.

In the Pentium 4 CPU, SSE2 instruction total 144,

SSE3 also a new addition of 13 new instructions for a video decoder, two threads for synchronization, and the rest for complex mathematical operations .

SSE4 has increased by 50 new help compiler, media, character / text processing program and point to an acceleration command.

Reference: http://www.360doc.com/content/15/0411/07/21966267_462329844.shtml brief history of the development of Intel CPU

Reference: https://baike.baidu.com/item/ Instruction Set / 238,130 instruction set

ARM instruction set

ARM There were three kinds of instruction sets: ARM instruction set , Thumb instruction set and the Thumb-2 instruction set. The specific use of what instruction set chip ARM V?

Reference: https://www.cnblogs.com/voidobject/p/3975552.html

Median OS / CPU architecture median / instruction set of bits / upward compatible

The median is the operating system on which it depends, said the number of bits instruction set.

32-bit CPU: a data bus (Databus) has 32 data bits ALU can handle.

Down (before) compatible

Forward-compatible CPU, 64-bit CPU is compatible with 32-bit instruction set, so the 64-bit 32-bit CPU can run the operating system.

32-bit 16-bit instruction set compatible CPU, the CPU can run 32-bit 16-bit operating system.

How backward compatibility?

64-bit cpu from over 16 development is still x86 architecture, principles and basic instructions are the same.

bits 16; 16-bit code is compiled
mov eax, 1; machine code is: 66 b8 01 00 00 00

16 is programmed using the 32-bit register, the compiler will automatically add default operand-size override prefix (the default operand size override prefix).

bits 32; 32-bit code is compiled
mov eax, 1; machine code is: b8 01 00 00 00

Compilation of statements of this code is exactly the same, except for the 32-bit code and compiled machine code which is not the same.

操作64位寄存器的低32位，高32位会清0，例如mov eax, 0FFFFFFFCH,则整个寄存器为00000000FFFFFFFCH，高32位会被清0。

Reference: https://zhidao.baidu.com/question/329146909.html register how backward compatible?

Reference: http://book.51cto.com/art/201210/359658.htm general register

Reference: https://zhidao.baidu.com/question/2011537345660325628.html the CPU median, median OS

Instruction set of CPU selected language, the microarchitecture of specific implementations.

3. Core / micro-architecture (self-study architecture / public version of the schema)

Computer language "instruction set architecture" vs. Execution Language carriers of "micro-architecture processor core."

Can not decide instruction set architecture, x86 instruction set can also use the ARM architecture.

Instruction set version	Microarchitecture	use
ARM V1	ARM1
ARM V2	ARM2, ARM3
ARM V3	ARM6, ARM7
ARM V4	StrongARM, ARM7TDMI, ARM9TDMI
ARM V5	ARM7EJ, ARM9E, ARM10E, XScale
ARM V6	ARM11, ARM Cortex-M
ARM V7	ARM Cortex-A, ARM Cortex-M, ARM Cortex-R
ARM V8
ARM V9

ARM launched a common architecture, cache (cache) is in the kernel, the kernel also known as public version of the schema.

3.1ARM licensing model

ARM CPU provides two types of authorization:

3.1.1 core instruction set authorization

2016, Samsung released Exynos8 Octa 8890 (Octa on behalf of 8-core), which is Samsung's first self-developed own ARM chip architecture ''

Since self RESEARCH REVIEW architecture = microarchitecture ≈cortex-A53, A73 (public version microarchitecture)

Qualcomm, based on the depth of developing its own ARM v7 processor microarchitecture.

Apple, based on ARMv7 develop Swift microarchitecture.

3.1.2 kernel design scheme authorized

Most manufacturers choose to directly purchase ARM CPU core design, and then integrated with other components (such as the GPU, multimedia processing, modem, etc.), for producing a complete system-on-chip SoC.

reference:

https://blog.csdn.net/baidu_35679960/article/details/77606930 related instruction set architecture, arm cores, SoC, a processor, CPU, GPU, etc.

https://blog.csdn.net/zzx1045917067/article/details/78575259 ARM ARM instruction set version and version

Or based on existing infrastructure for secondary custom modifications, such as the Samsung Hummingbird Hummingbird core, etc. are modified based on the Cortex-A8. In 2011, Samsung officially launched Exynos4 Dual 4210 chip (Dual behalf of dual-core) and a corresponding new flagship phone Galaxy SII, as well as the "hummingbird" was renamed Exynos3 Single 3110 (single behalf of monocytes), which is after the beginning of the Exynos family .