Digital Design 2020-21 VHDL Coursework21

Digital Design 2020-21
VHDL
Coursework
1 Objectives
The objective of this assignment is to use VHDL to design and implement the processing required for
the control logic of a pedometer. The correctness of the design should be illustrated through
simulations.
2 Deliverables:
A report showing:
 A completed design for a pedometer using VHDL and targeted to an Artix7 FPGA.
 An explanation of the design decisions and testing methodologies.
 A set of simulations showing the correct operation of the design.
3 Assignment Specification
A pedometer is a wearable device that detect footsteps automatically and, from this
information, can estimate distances travelled, speed etc. In a complete system, the input to the
processor would come from an accelerometer detecting footsteps. For the purpose of this
exercise, the input will be simulated by one of the push buttons on the Nexys4 FPGA board.