Digital Design 2020-21
Finite State Machines Coursework
1 Objectives
The objective of this assignment is to design a synchronous finite state machine and to
demonstrate the correctness of the design through simulations in VHDL or Verilog.
2 Deliverables:
i) A completed design for a synchronous finite state machine, including a suitable
choice of state encoding and a set of Boolean equations for the state transition
function and the output function.
ii) A VHDL or Verilog language implementation of the finite state machine,
including simulations.
iii) A report showing design decisions and testing methodologies.
3 Assignment Specification
A synchronous finite state machine has a single 1-bit wide ‘Serial Data’ input (SD) and a
single output (T). The output changes on the rising edge of the clock pulse, as shown in
Figure 1.
Figure 1: Synchronous finite state machine timing diagram
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