序列检测-移位寄存器+FSM

要求：检测10010
实现方案一：移位寄存器

module seqchk(
input x,
input clk,
input rst_n,
output z,
output [4:0]q);
reg [4:0]q;
reg [4:0]q_dly;
//将串行数据转为并行，再检测与目标数据是否一致
always @(posedge clk or negedge rst_n)
if(!rst_n) q <= 5'b0;
else q_dly <= q;
// 将q的数据延迟一个clk，使得z和x对齐
assign q_dly = {
    
    q[3:0],x}
assign z = {
    
    q_dly == 5'b10010}:1:0;
endmodule

实现方案二：三段MOORE状态机

module seqchk(
input clk,
input x,
input rst_n,
output z);
reg [2:0] cur_state;
reg [2:0] nxt_state;

parameter 	S0 = 3'b0,
			S1 = 3'b1,
			S2 = 3'b2,
			S3 = 3'b3,
			S4 = 3'b4,
			S5 = 3'b5,
			S6 = 3'b6;
always @(posedge clk or negedge rst_n)
if(!rst_n) cur_state <= 3'b0;
else cur_state <= nxt_state;

always @(posedge clk or negedge rst_n)
if(!rst_n) nxt_state <= 3'b0;
else begin
case(cur_state)
S0: if(x == 1) nxt_state = S1;
else nxt_state = S0;
S1: if(x == 1) nxt_state = S2;
else nxt_state = S0;
S2: if(x == 0) nxt_state = S3;
else nxt_state = S1;
S3: if(x == 0) nxt_state = S4;
else nxt_state = S1;
S4: if(x == 1) nxt_state = S5;
else nxt_state = S0;
S5: if(x == 0) nxt_state = S6;
else nxt_state = S1;
S6: nxt_state = S0;
default: nxt_state = S0;
endcase
end

assign z = (cur_state == S6)?1:0;
endmodule