SystemVerilog - Interface

Interface (Interface) is an important part of the new SystemVerilog, specifically for the interaction between the package module. Interface also helps design reuse. Interface is a hierarchical structure that can contain other interfaces.
Here are some advantages of using the interface:

• Connectivity interface package, the same interface may be used as a single component, which can replace one set of a conventional model name. This simplifies the code connected to the port, help maintain and increase readability.
• Functional interface package, through the successive module interface, may be more easily divided. Thus, the level of abstraction and granularity interactive protocol can be optimized independently of outside modules.
• Interfaces can contain parameters, constants, variables, functions and tasks, as well as process and continuous assignments. This not only helps the system-level modeling, but also conducive to TB applications.
• Interface helps to establish functional coverage of records and reports, inspection protocols and applications such assertions.
• An interface for accessing the Port-less, an interface module in the embodiment may be directly into static data objects. Thus, the interface access method for internal state information related to may be called at various points in time, to share information.
• Flexibility, the interface module can be like as parameterized. Similarly, when a head module can be established with the embodiment of the interface is not specified, the original called interfaces. This interface can be specified when the back of the module embodiment.
  Briefly, the interface is named a bundle of wire mesh, similar to the structure, in addition to the interface port may not be used as the structure of the module.
  The following example shows the definition and use of the interface:

// Interface definition
interface Bus;
	logic [7:0] Addr, Data;
	logic RWn;
endinterface

// Using the interface
module TestRAM;
	Bus TheBus(); // Instance the interface
	logic [7:0] mem [0:7];
	RAM TheRAM (.MemBus(TheBus)); // Connect it
	initial 
	begin
		TheBus.RWn = 0;
		TheBus.Addr = 0;
		for (int I=0; I<7; I++)
			TheBus.Addr = TheBus.Addr + 1;
		TheBus.RWn = 1;
		TheBus.Data = mem[0];
	end
endmodule

module RAM(Bus MemBus);
	logic [7:0] mem[0:255];
	always @*
		if (MemBus.RWn)
			MemBus.Data = mem[MemBus.Addr];
		else
			mem[MemBus.Addr] = MemBus.Data;
endmodule

Interface port (Interface Ports)
interfaces can also have an input port, an output port and the bidirectional port. Only declare variables and the line in the list of port to be instantiated when the port is connected to the outside by name or position. Interface can be shared with the interface. Port of use ANSI style statement.
The following example shows the interface port with a clock:

interface ClockedBus (input Clk);
	logic [7:0] Addr, Data;
	logic RWn;
endinterface

Module RAM (ClockedBus Bus);
	always @（posedge Bus.Clk)
		if (Bus.RWn)
			Bus.Data = mem[Bus.Addr];
		else
			mem[Bus.Addr] = Bus.Data;
endmodule

// Using the interface
module Top;
	reg Clock;
	// Instance the interface with an input, using named connection
	ClockedBus TheBus (.Clk(Clock));
	RAM TheRAM (.Bus(TheBus));
	...
endmodule

Parameterization interface (Parameterised Interface)
The following is a simple example of the parameterization interface of the display:

interface Channel #(parameter N=0)
		(input bit Clock, bit ACK, bit Sig);
	bit Buff[N-1:0];
	initial 
		for (int i=0; i<N; i++)
			Buff[i] = 0;
	always @ (posedge Clock)
		if (Ack == 1）
			Sig = Buff[N-1];
		else
			Sig = 0;
endmodule

// Using the interface
module Top;
	bit Clock, Ack, Sig;
	// Instance the interface. The parameter N is set to 7 using named
	// connection while the ports are connected using implict connection 
	Channel #(.N(7)) TheCh (.*);
	TX TheTx (.Ch(TheCh));
	...
endmodule

Adjust the interface port (Modports in Interface)

A member associated with the interfaces add to the mix: adjusting port. This interface module to provide information on the direction and control of the tasks and functions in a particular module.
This example involve adjusting port, for determining the direction of the signal interface. Direction from the point of view of the module in our example is TheRAM

interface MSBus (input Clk);
  logic [7:0] Addr, Data;
  logic RWn;
  modport Slave (input Addr, inout Data);
endinterface

module TestRAM;
  logic Clk;
  MSBus TheBus(.Clk(Clk));
  RAM TheRAM (.MemBus(TheBus.Slave));
  ...
endmodule

module RAM (MSBus.Slave MemBus);
  // MemBus.Addr is an input of RAM
endmodule

Interface tasks (Tasks in Interfaces)

Tasks and functions can be defined in the interface, to achieve a more abstract modeling. The following example shows two tasks used to model the function of the bus. Task called testRAM module.

interface MSBus (input Clk);
  logic [7:0] Addr, Data;
  logic RWn;

  task MasterWrite (input logic [7:0] waddr,
                    input logic [7:0] wdata);
    Addr = waddr;
    Data = wdata;
    RWn = 0;
    #10ns RWn = 1;
    Data = 'z;
  endtask

  task MasterRead (input  logic [7:0] raddr,
                   output logic [7:0] rdata);
    Addr = raddr;
    RWn = 1;
    #10ns rdata = Data;
  endtask
endinterface

module TestRAM;
  logic Clk;
  logic [7:0] data;
  MSBus TheBus(.Clk(Clk));
  RAM TheRAM (.MemBus(TheBus));
  initial
  begin
    // Write to the RAM
    for (int i = 0; i<256; i++)
      TheBus.MasterWrite(i[7:0],i[7:0]);

    // Read from the RAM
    for (int i = 0; i<256; i++)
    begin
      TheBus.MasterRead(i[7:0],data);
      ReadCheck : assert (data === i[7:0])
        else $error("memory read error");
    end
  end
endmodule