SystemVerilog learning (2)-interface to build a test platform

interface

SystemVerilog uses interfaces to model the communication between blocks. The interface can be seen as a bundle of intelligent connections. The interface includes the function of connecting and synchronizing the communication between two or more blocks. They connect the design block and the test platform.

The clock and reset can be part of the interface statement, or an independent internal port.

The advantages of using the interface:
(1) The interface is easy to design and reuse: When there are multiple sets of bus connections with the same communication protocol in the design, the interface should be considered, such as multiple sets of AXI4 bus, AXIS bus;
(2) A new signal should be added When, you only need to declare it once in the interface, not in other modules.

Program example

The following program demonstrates the use of interface and task. The interface is defined in tb. The definition of the interface can be placed in a separate .sv file in the actual project.

adder.v

`timescale 1ns / 1ps

// Company: 
// Engineer: 
// 
// Create Date: 11/27/2020
// Author Name: Sniper
// Module Name: adder
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 


module adder(
    input clk,
    input rst_n,
    input [7:0] a,
    input [7:0] b,
    input write_en,
    output reg [8:0] p,
    output reg out_en
);

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
    begin
		p <= 0;
        out_en <= 0;
    end
	else
    begin
        if(write_en)
        begin
            p <= a + b;
            out_en <= 1;
        end
        else
            out_en <= 0;
    end
end

endmodule

tb_adder.sv

`timescale 1ns / 1ps

// Company:
// Engineer:
//
// Create Date: 11/27/2020
// Author Name: Sniper
// Module Name: tb_adder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//


interface adderInterface(input bit clk, input bit rst_n);
    //write in
    logic [7:0] a;
    logic [7:0] b;
    logic write_en;
    //output
    logic [8:0] p;
    logic out_en;

    //task
    task init;
    begin
        a = 0;
        b = 0;
        write_en = 0;
    end
    endtask

    task write(input [7:0] data_a, input [7:0] data_b);
    begin
        @(posedge clk);
        write_en <= 0;
        a <= data_a;
        b <= data_b;

        @(posedge clk);
        write_en <= 1;

        @(posedge clk);
        write_en <= 0;
    end
    endtask
    
    task catch;
    begin
        @(posedge clk);
        if(out_en)
        begin
            $display("Catch one output: %0d ", p);
        end
    end
    endtask
endinterface



module tb_adder;

//system signals
reg clk;
reg rst_n;

//interface
adderInterface adder_if(clk, rst_n);


initial
begin
    clk = 0;
    rst_n = 0;

    adder_if.init;

    repeat(10) @(posedge clk);
    rst_n <= 1;

    for(int i=0;i<8;i++)
        adder_if.write(2,i);

end

initial
begin
    forever adder_if.catch;
end


//clock
always #5 clk = ~clk;


//DUT
adder DUT
(
    .clk(clk),
    .rst_n(rst_n),
    .a(adder_if.a),
    .b(adder_if.b),
    .write_en(adder_if.write_en),
    .p(adder_if.p),
    .out_en(adder_if.out_en)
);

initial
begin
  $dumpfile("curve.vcd");
  $dumpvars(0,DUT);
end

initial #1000 $finish;

endmodule

operation result

[IC@IC sim]$ vcs -R -sverilog ../rtl/adder.v ../bench/tb_adder.sv -l run.log

...

Catch one output: 2 
Catch one output: 3 
Catch one output: 4 
Catch one output: 5 
Catch one output: 6 
Catch one output: 7 
Catch one output: 8 
Catch one output: 9 
$finish called from file "../bench/tb_adder.sv", line 123.
$finish at simulation time              1000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 1000000 ps
CPU Time:      0.140 seconds;       Data structure size:   0.0Mb
...

[IC@IC sim]$