Introduction to package in SystemVerilog

1. The definition of the package:

package 包名;     

endpackage

A package is an independent declaration space, and multiple modules share user-defined types.

2. Synthesizable structure that can be included in the package:

1) Parameter and localparam constant definitions;
2) const defines variables as constants;
3) typedef user-defined types;
4) automatic task and function definitions (must be declared as automatic, and storage area will be allocated each time it is called for easy integration);
5 ) Import statements from other packages;
6) Operator overloading definition.

3. How to quote the package:

1) Use the scope resolution operator to ::directly quote;
2) Import specific sub-items in the package into the module or interface;
3) Use wildcards to *import the sub-items in the package into the module or interface;

Four, for example:

package definitions;

    parameter Version = "1.1";
    typedef enum  {
    
    ADD,SUB,MUL} opcode_t;
    typedef struct{
    
    
        logic [31:0]a,b;
        opcode_t opcode;
    } instruction_t;

    function automatic [31:0]multiplier(input [31:0]a,b);

        return a*b;
      
    endfunction

endpackage

Direct reference method:

module ALU( input definitions::instruction_t IW,
            input logic clock,
            output logic [31:0]result);

            always_ff @(posedge clock) begin
                case(IW.opcode)
                    definitions::ADD:result = IW.a+IW.b;
                    definitions::SUB:result = IW.a-IW.b;
                    definitions::MUL:result = definitions::multiplier(IW.a,IW.b);
                endcase
                
            end
endmodule

Use import to introduce:

module  ALU(input definitions:: instruction_t  IW ,
 			input  logic clock,
 			output logic [31:0] result);

		import definitions:: ADD;
		import definitions:: SUB;
		import definitions:: MUL;
		import definitions:: multiplier;
		always_comb begin
		   case (IW.opcode)
		   ADD: result = IW.a +IW.b;
		   SUB: result = IW.a -IW.b;
		   MUL: result = multiplier(IW.a, IW.b);
		   endcase
		end
endmodule

More than four lines of import import code, the following may be used testbenchin import definitions:: *;place of, i.e. all sub-keys into disposable, and can be used directly, such as ADD, but not written definitions::ADD.

import definitions：：*；
	module  tb_ALU;
	instruction_t  test_word ;
	logic [31:0] alu_out;
	logic  clock = 0;
	ALU dut(.IW(test_word), .result(alu_out), .clock(clock));
	always #10 clock = ~clock;
	initial begin @(negedge clock)
	          test_word.a = 5;
	          test_word.b =7;
	          test_word.opcode = ADD;
	          @(negedge clock)
	          $display(“alu_out = %d (expected 12)”, alu_out);
	          $finish;
	end
endmodule