Introduction to interface in SystemVerilog

One, the definition and instantiation of interface

interface main_bus;
  wire [15:0]  data;
  wire [15:0]  address;
  logic[7:0]   bus_request;
endinterface

module top()
   main_bus bus(); //接口实例化
   slave slave1(
    .bus(bus));
endmodule

Second, the characteristics of interface

Interface is a powerful port type:

1. It can simplify the modeling and verification of complex designs.
2. It can be defined separately outside the module.
3. Support multiple signals to form a port, only need to declare once.
4. The interface can include port, task, function, process block, program block, and can also be parameterized.

3. The difference and connection between interface and module:

1) The interface cannot contain design levels; it can have input and output signals.
2) The interface can be used as the port of the module (when used as a port), indicating the communication channel between the modules.
3) The interface can contain modport (module port abbreviation), and the module connected to the interface can access the interface in different ways. That is, either interface can be passed to the module, or only the specific port defined by modport can be passed to the module.

Four, for example

RTL

interface ticket_if(input logic clk,rst_n,[5:0]m_in,output logic ticket_out,[5:0]m_out);
    
    logic [5:0]sum;

    task change(input logic [5:0]in_data,
                          output logic [5:0]out_data );
                          
             out_data = in_data - 6;
    endtask //automatic

    modport ticket_ports(input clk,rst_n,m_in,
            output ticket_out,m_out,sum,
            import task change(input logic [5:0]in_data,
                               output logic [5:0]out_data )
            );
endinterface //interfacename


module ticket(ticket_if.ticket_ports ports);

enum logic [1:0]{
    
    s0,s1,s2} state_c,state_n;

always_ff @(posedge ports.clk or negedge ports.rst_n) 
     
    if(!ports.rst_n)
        state_c <= s0;
    else
        state_c <= state_n;
        
always_comb       
    case(state_c)
        s0:begin
            ports.sum = ports.m_in;
            ports.ticket_out = 0;
            if(ports.sum>=6)
                state_n <= s2;
            else
                state_n <= s1;
        end
        s1:begin
            ports.sum = ports.sum + ports.m_in;
            if(ports.sum>=6)
                state_n <= s2;
            else
                state_n <= state_c;
        end
        s2:begin
            ports.change(ports.sum,ports.m_out);
            //ports.m_out = ports.sum - 6;
            ports.ticket_out = 1;
            state_n <= s0;
        end
        default:state_n <= s0;
    endcase

endmodule

testbench

module tb_ticket;

	timeunit 1ns;
	timeprecision 100ps;
	
	
	logic clk,rst_n;
	logic [5:0]m_in;
	logic ticket_out;
	logic [5:0]m_out;
	
	initial
	  begin
	      clk = 0;
	      rst_n = '1;
	      #5 rst_n = '0;
	      #5 rst_n = '1;
	  end
	  
	initial
	  begin
	      #10 m_in=2;
	      #10 m_in=3;
	      #10 m_in=4;
	      #10 m_in=5;
	      #10 m_in=6;
	      #10 m_in=7;
	      #10 m_in=8;
	  end
	
	always #5 clk = ~clk;
	
	//ticket_if ports(.*);
	ticket_if ports(clk,rst_n,m_in,ticket_out,m_out);
	ticket u_ticket(ports.ticket_ports);
endmodule