[SystemVerilog] define compilation problems

Defines an enumerated type in top_define.svh in the top_define.svh

`ifndef TOP_DEFINE__SVH
`define TOP_DEFINE__SVH

typedef enum bit[2:0] {TOP_HIB,TOP_BG,TOP_GS} FSM_STATE;

typedef struct {bit[63:0] data; bit[7:0] ctrl} TR;

`endif

If you want to FSM_STATE with the interface and driver, package how to write it?

`ifndef AA_AGENT__SVH
`define AA_AGENT__SVH

   `include "top_define.svh"
   `include "aa_if.sv"

   package aa_pkg;
     import uvm_pkg::*;
     `include "aa_driver.sv"
     ...
   endpackage

The above wording to ensure aa_if.sv can see top_define.svh, but aa_driver.sv not see, because there is no aa_pkg to include in;

`ifndef AA_AGENT__SVH
`define AA_AGENT__SVH

   `include "top_define.svh"
   `include "aa_if.sv"

   package aa_pkg;
     import uvm_pkg::*;
     `include "top_define.svh"
     `include "aa_driver.sv"
     ...
   endpackage

The above written driver can not see top_define.svh, because for the first time include "top_define.svh" has been compiled in the second encounter in due top_define.svh

Plus `ifndef AA_AGENT__SVH, it will not be compiled, resulting in driver can not see.

solution：

package top_define_pkg;

   `include "top_define.svh"
endpackage

`ifndef AA_AGENT__SVH
`define AA_AGENT__SVH

   `include "top_define_pkg.svh"
   import top_define_pkg::*;

   `include "aa_if.sv"

   package aa_pkg;
     import uvm_pkg::*;
     import top_define_pkg::*;
     `include "aa_driver.sv"
     ...
   endpackage

The top_define.svh into a single package Package, and if so employed import mode driver can eat top_define.svh; import because compiled would stuff in, regardless of whether the compiled, and include different ways.