SystemVerilog constraint is disabled (SystemVerilog Disable Constraints)

By default, all constraints are enabled, and the randomization process, SystemVerilog constraint solver will take into account all the constraints. Do not consider disabled constrained randomization process.

You can enable or disable the constraints by constraint_mode ().

Syntax

Constraint_mode () can be used as both tasks can also be called as a function.

When a task calls, the method does not return anything. The input parameters provide a task to open or close the given constraints. When a function call, the method returns to the current state of the given constraints.

// Called as a task
class_obj.const_name.constraint_mode(0);       // Turn off the constraint
class_obj.const_name.constraint_mode(1);       // Turn on the constraint
 
// Called as a function
status = class_obj.const_name.constraint_mode();   // status is an int variable to hold return value

constraint_mode () is a built-in method, can not be covered!

method

The following table shows the time when the task is called constraint_mode, each value indicating what input parameters.

Case

In the following example, we will see constraint_mode () What is the impact of its constraints.

class Fruits;
  rand bit[3:0]  num;         // Declare a 4-bit variable that can be randomized
 
  constraint c_num { num > 4;      // Constraint is by default enabled, and applied
                    num < 9; };   // during randomization giving num a value between 4 and 9
endclass
 
module tb;
  initial begin
    Fruits f = new ();
 
  // 1. Print value of num before randomization
    $display ("Before randomization num = %0d", f.num);   
 
    // 2. Call "constraint_mode" as a function, the return type gives status of constraint
    if (f.c_num.constraint_mode ())
      $display ("Constraint c_num is enabled");
    else
      $display ("Constraint c_num is disabled");
 
    // 3. Randomize the class object
    f.randomize ();
 
    // 4. Display value of num after randomization
    $display ("After randomization num = %0d", f.num);    
  end
endmodule
 
Simulation Log
ncsim> run
Before randomization num = 0
Constraint c_num is active
After randomization num = 8
ncsim: *W,RNQUIE: Simulation is complete.

Now, let's try to use constraint_mode trying to make variable before randomization () constraint is disabled.

module tb;
  initial begin
    Fruits f = new ();
    $display ("Before randomization num = %0d", f.num);   
 
    // Disable constraint 
    f.c_num.constraint_mode(0);
 
    if (f.c_num.constraint_mode ())
      $display ("Constraint c_num is enabled");
    else
      $display ("Constraint c_num is disabled");
 
    // Randomize the variable and display
    f.randomize ();
    $display ("After randomization num = %0d", f.num);    
  end
endmodule
 
Simulation Log
ncsim> run
Before randomization num = 0
Constraint c_num is disabled
After randomization num = 15
ncsim: *W,RNQUIE: Simulation is complete.

Note that closing any value constraint solver will choose variable support rather than the value of the limit specified in the constraint range.

If you call constraint_mode () constraint does not exist on the way, it will cause a compiler error.

 module tb;
    initial begin
      Fruits f = new();
      f.c_does_not_exist.constraint_mode(1);
    end
  endmodule

Simulation Log
	f.c_does_not_exist.constraint_mode (1);
                     |
ncvlog: *E,NOTCLM (testbench.sv,11|21): c_does_not_exist is not a class item.

参考文献：
【1】https://www.chipverify.com/systemverilog/systemverilog-disable-constraints