1. Brief description
I have been employed for two months, and I have used System Verilog for verification. Before writing testbench directly in Verilog, after using sv during this period, I found that it is really necessary to switch to sv for verification.
2. Body
1) Data type
| Types of | description | symbol |
|---|---|---|
| logic | Four states, equivalent to Verilogreg and wire functions | |
| bit | Dual state, custom bit width | Unsigned by default |
| int | Dual state, 32bit | Signed |
| byte | Dual state, 8bit | Signed |
| shortint | Dual state, 16bit | Signed |
| longint | Dual state, 64bit | Signed |
| integer | Four states, 32bit | Signed |
| time | Four states, 64bit | Unsigned |
| real | Dual state, 64bit | Double precision floating point, equivalent to double |
| shortreal | Dual state, 32bit | Equivalent to float |
Note:
- The four states are: 0, 1, x, and z; the dual states are: 0, 1.
- In Verilog, reg type data can only be assigned in always, and assign to use wire type. In sv, logic can be assigned in always or used in assign, but it cannot be driven in multiple places.
2) Fixed-width array
int array0[0:15]; //16个整数
int array1[16]; //16个整数
int array2[0:7][0:3]; //二维数组
int array3[8][4]; //二维数组
array3[5][2]=1; //数组赋值
bit [7:0] unpack[3]; //非合并数组，分配三个字空间，但只存放低字节
int ascend[4]=`{0,1,2,3};//常量数组前面加 “ ` ”
3) Array operation
initial begin
bit [31:0] src[5],dst[5];
for(int i=0;i<$size(src);i++)
src[i] = i;
foreach(dst[j])
dst[j]=src[j]*2;
end
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