Table of contents
1 Introduction
In FPGA applications, data caching is a major focus. Whether it is image processing, AD acquisition, or PCIE, etc., data needs to be cached for subsequent processing. Ordinary FPGAs can mount SDRAM, DDR3, DDR4 and other memory particles as caches. media, but sometimes limited to IO ports, FPGA models and other reasons, it is also necessary to design SODIMMs to adapt to additional memory sticks to meet the needs of data caching, which is generally used for high-end projects;
This article uses Xilinx's V7 FPGA development board NetFPGA-SUME platform as the experimental board. The development board has 2 SODIMM interfaces on board and can be inserted into 2 memory sticks as a cache. The FPGA development board can be purchased from public channels on the Internet; this routine Use the HDMI input video or the internally generated color bar video as the video source, cache the video in the SODIMM memory stick for three-frame image buffering, and then read it out and send it to the HDMI display to verify whether the FPGA reads and writes to the SODIMM memory stick successfully. If If the output image is chaotic or the quality is not high, it proves that the reading and writing is wrong, otherwise it is successful; this blog describes in detail the design scheme of FPGA using SODIMM memory interface. The engineering code can be comprehensively compiled and debugged on the board, and can be directly transplanted. Project development for current students and graduate students is also suitable for on-the-job engineers to do learning improvement, and can be applied to high-speed interfaces or image processing fields in medical, military and other industries; provide complete and smooth engineering source code
and technical support;
engineering source code and technology The way to obtain support is at the end of the article, please be patient and read to the end;
disclaimer
This project and its source code are partly written by myself, and partly obtained from public channels on the Internet (including CSDN, Xilinx official website, Altera official website, etc.). The project and its source code are limited to the personal study and research of readers or fans, and commercial use is prohibited. If the legal issues caused by the commercial use of readers or fans for their own reasons have nothing to do with this blog and the blogger, please use it with caution. . .
2. Introduction to SODIMM memory stick
The SODIMM interface is an old-fashioned memory stick interface. It is said that it is old-fashioned for computer motherboards, especially compact notebook motherboards. Because of the large size of the SODIMM interface, it has now become popular to the M.2 interface, but for FPGAs, SODIMM The interface is not outdated. After all, generally speaking, the memory requirement of FPGA is not as large as that of a computer. The addition of a SODIMM interface memory stick is already a top configuration. There is a special explanation about SODIMM memory sticks on the Internet. I will not be wordy here. It is recommended An article, the link is as follows:
Click to go directly
3. Design thinking framework
The design framework is as follows:
video input
My development board has an FMC interface on board, and I happen to have an FMC adapter board for HDMI input and output. The HDMI input interface is connected to a silcom9011 chip as an HDMI decoder, which decodes the input HDMI video TMDS differential video to 24bit The GRB video is for FPGA use; the silcom9011 chip requires i2c configuration to be used. This routine provides the i2c controller configuration silcom9011 implemented by verilog source code. For the detailed configuration and use of silcom9011, please see my previous special blog. The address is as follows: Click
Direct Go to
the HDMI output interface and connect a silcom9134 chip as an HDMI encoder to encode the input 24bit GRB video into TMDS differential HDMI video output; so the video input can use the input HDMI interface; but some brother boards may not have HDMI input interface, Therefore, I specially designed a dynamic color bar video generated inside the FPGA to simulate the input video, and it can also be used as a video source to participate in the test. The input can still be verified by observing the dynamic changes of the color bar; the choice of the two is through the top layer of the project source code. `define COLOR_TEST to select, the selection switching logic is as follows:
`ifdef COLOR_TEST
assign ud_w_0_ud_wclk =vout_clk ;
assign ud_w_0_ud_wde =video_de_color ;
assign ud_w_0_ud_wvs =video_vs_color ;
assign ud_w_0_ud_wdata=video_rgb_color;
`else
assign ud_w_0_ud_wclk =vin_clk ;
assign ud_w_0_ud_wde =vin_de ;
assign ud_w_0_ud_wvs =vin_vs ;
assign ud_w_0_ud_wdata=vin_data;
`endif
If `define COLOR_TEST is commented out at the top layer, the input video source is the HDMI input interface;
If `define COLOR_TEST is not commented out at the top level, the input video source is a dynamic color bar;
The interface of the dynamic color bar top-level module is as follows:
video cache
Use my classic routine FDMA to complete. FDMA is a controller specially used for reading and writing DDR of various types of data. It is also very convenient to use it to cache video. For the special explanation of FDMA, please see my previous special blog, the address is as follows :
Click to go directly to
MIG configuration calling SODIMM memory module
SODIMM memory sticks are essentially DDR3 particles, and Xilinx provides a dedicated MIG IP core as a PHY to interact with it, but MIG configuration calling SODIMM memory sticks is not the same as the traditional one; the key points are as follows: Other configurations are based on your own memory stick
model Just select;
my board memory is as follows:
VGA timing
Since the output video resolution is 1920x1080@60Hz; therefore, it is necessary to provide a standard VGA timing driver to form a video stream. The routine provides a VGA timing module of verilog source code. The modified module supports 7 commonly used resolutions, and can be modified through the defined macro definition. , as follows:
This design uses 1080P timing;
video output
My development board has an FMC interface on board, and I happen to have an FMC adapter board for HDMI input and output. The HDMI input interface is connected to a silcom9011 chip as an HDMI decoder, which decodes the input HDMI video TMDS differential video to 24bit The GRB video is used by the FPGA; the HDMI output interface is connected to a silcom9134 chip as an HDMI encoder, and the input 24bit GRB video is encoded as a TMDS differential HDMI video output; the silcom9134 chip needs i2c configuration to use, this routine provides verilog source code implementation The i2c controller is configured with silcom9134. For the detailed configuration and use of silcom9134, please see my previous special blog. The address is as follows:
Click to go directly
4. Detailed explanation of vivado project
Development board FPGA model: Xilinx–V7–xc7vx690tffg1761-3;
development environment: Vivado2019.1;
input: HDMI video or dynamic color bars, resolution 1920x1080@60Hz;
output: HDMI video, resolution 1920x1080@60Hz;
application: FPGA use SODIMM memory stick;
the project Block Design is as follows:
the project code structure is as follows:
FPGA resource consumption and power consumption estimation after comprehensive compilation is as follows:
5. Board debugging and verification
The board is as follows:
HDMI interface output is as follows:
Dynamic color bar output is as follows:
Take dynamic color bar output as an example, see the output demonstration video:
FPGA MIG configuration SOMIDD memory module
6. Welfare: acquisition of engineering code
Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a certain degree network disk link. The
method of data acquisition: private, or the V business card at the end of the article.
The network disk information is as follows:
