Power integrity of the PCB circuit design

　　In the case of circuit design in general, we are very concerned about the quality of the signal, but sometimes we tend to be confined to the signal line of research, and the power and ground as the ideal to deal with, although doing so can simplify the problem, but in high-speed design in this simplification has not work the. Although a direct comparison of the results of the circuit design is manifested from the signal integrity, but we must not be ignored power integrity design. Because the power supply signals directly affect the integrity of the final integrity PCB board. Both power and signal integrity integrity are closely related, and in many cases, mainly due to the influence of signal distortion is a power supply system. For example, ground bounce too much noise, decoupling capacitor design inappropriate, very serious impact loop, multi-split power / ground plane is not good, the formation unreasonable design, nonuniform current and the like.
　　1) power distribution system
　　power integrity design is a very complex matter, but in recent years how to control impedance between the power supply system (power and ground planes) are key to the design. Theoretically, the impedance between the power supply system as low as possible, the lower the impedance, the smaller the amplitude of the noise, the less voltage loss. The actual design, we can hope to achieve our target impedance is determined by a predetermined maximum voltage and power range, and then, by adjusting factors in the impedance of the circuit of each part of the power supply system (frequency dependent) impedance to approximate a target.
　　2) to bounce
　　when the edge rate is less than 0.5ns high-speed devices, data exchange rate from the large-capacity data bus particularly fast, when it is sufficient to affect the signal generating strong ripple in the power supply layer, it will produce power instability problems . When the current change through the loop, since the loop inductance produces a voltage when the shorter rising, the current change rate increases, the ground bounce voltage increases. At this time, the ground plane (ground) is not over the zero level, and the DC power is not an ideal position. When the increased gate switched simultaneously, ground bounce becomes more serious. For a 128-bit bus, there may be a 50_100 I / O line switching at the same clock edge. In this case, while switching back to the I / inductance of the power and ground loops O drivers must be as low as possible, otherwise, connected to the same ground a voltage will appear stationary brush. Rebound everywhere, chip, package, circuit board or the connector has a ground bounce may occur, resulting in power integrity problems.
　　From the development point of view of technology, the device will only reduce the rising edge, the width of the bus will only increase. The only way to maintain an acceptable ground bounce is to reduce power and ground distributed inductance. For chip, it means to move a wafer array, as many power and ground placement, and connection to the package as short as possible to minimize inductance. For, packaging, packaging means moving layer, the pitch of the ground plane closer to the power supply, as used in the BGA package. The connector, means to use more connector pins or redesigned to have the internal power and ground planes, such as on the cord strip connector. The circuit board, which means that adjacent power and ground planes as close as possible. Since the inductance is proportional to the length, so as to make wiring short power and ground noise will be reduced.
　　3) decoupling capacitor
　　we all know add some capacitor between the power supply and the ground can reduce the noise of the system, but in the end how much capacitance added to the circuit board? How much of each capacitor's value appropriate? Each capacitor on what position more good? similar problems we generally did not go seriously considered, but with the designer's experience to carry out, and sometimes even think capacitance as possible. In high-speed designs, we must consider the parasitic capacitance coupled out quantitative counting the number of capacitors and the capacitance value of each capacitor and the specific location of placement, to ensure that within the control range, a basic principle of the impedance of the system decoupling capacitor is needed, one less, the excess capacitance, a do not. More on PCB-related knowledge to do in the Czech Republic with the official website www.jiepei.com/G602, welcome to learn together!