PCI-Express (peripheral component interconnect express) is a high speed serial computer expansion bus standard, its original name was "3GIO", was presented by Intel in 2001, it is intended to replace older PCI, PCI-X and AGP bus standard.
Belonging to the high-speed serial PCIe dual-channel high-bandwidth transmission point, the connected device is assigned exclusive channel bandwidth is not shared bus bandwidth, to support the main active power management, error reporting, reliability of the transmission end to end quality of service and hot-swap ( QOS) and other functions.
PCI-SIG PCIe handed over after (PCI Special Interest Organization) certification issued renamed "PCI-Express", referred to as "PCI-E". Its main advantage is the high data transfer rate, currently the highest version 16X 2.0 up to 10GB / s, but there is considerable potential for development.
PCI Express also has a variety of specifications from the PCI Express 1X PCI Express 32X, to meet the needs of low-speed devices occur within a certain time and the future high-speed equipment. PCI-Express interface is the latest PCIe 3.0 interface, the bit rate of 8GB / s, about twice the bandwidth generation, and comprises a transmitter and a receiver equalizer, the PLL clock and data recovery to improve a series of important new function, to improve data transmission performance and data protection.
INTEL, IBM, LSI, OCZ, Samsung (the plan), SanDisk, STEC, SuperTalent and Toshiba (the plan), etc., and for massive data growth enables users to larger, more powerful system scalability of the application, the latest addition to the LSI PCIe 3.0 technology MegaRAID controller and HBA products of excellent performance, you can achieve greater system design flexibility. Of course, the mainstream motherboard can support PCI Express 1.0 16X, as well as some higher-end motherboard supports PCI Express 2.0 16X.
PCIe standard
PCI Express Card for its physical size or more slots (× 16 used as the largest), but may not be suitable for smaller PCI Express slot; for example, the card may not be suitable × 16 × 4 × 8, or slots. Some slot using open outlet to allow a longer physically card, and negotiate the best electrical and logical connections.
The actual number of channels connected to the slot may be smaller than the number of physical slots supported size. One example is a slot can run × 16 × 1, × 2, × 4, × 8, × 16 card when the card is only run × 4 4 channels. The specifications can be read as "× 16 (× 4 mode)", and "× size @ × speed" symbol ( "× 16 @ × 4") are also common. Advantage is that the socket can accommodate a wider range of PCI Express card, motherboard hardware without the need to support the full transmission rate.
Card itself to design and manufacture a variety of sizes. For example, a solid state drive (SSD) appears to PCI Express card form generally used HHHL (half-height, half-length) and FHHL (full height, half-length) used to describe the physical dimensions of the card.
PCIe routing rules
1, from the edge to cheat traces PCIE chip pins should be limited to a length of 4 inches (about 100MM) or less.
2, the PCIE PERP / N, PETP / N, PECKP / N is three differential pairs of lines, to protect the distance between the (differential pair, and the distance of all the non-differential signal is 20Mil PCIE, to reduce the harmful effects of crosstalk and electromagnetic interference (EMI) the chip PCIE signal line and negative signal line to avoid high frequency, preferably the whole GND).
3, two differential pair take up the line length difference 5MIL. Each part of the two traces are required to match the length. 7 MIL line width difference, a differential pair of two take the line spacing is 7MIL.
4, when the PCIE signal trace layer change, should be placed on the ground near the signal via the signal via hole, each pair of signal 1-3 is recommended to set the signal via. PCIE using vias 25/14 differential pair, and two through holes must be placed symmetrically to each other.
5, PCIE require AC coupling between a transmitting end and a receiving end, two differential pair AC coupling capacitor must have the same package size, and position to be placed near the symmetry Goldfinger side, the capacitance value is recommended 0.1uF .
6, SCL signal line can not cross the other main chip PCIE.
