Table of contents
1. Introduction to PCIe equalization technology (summary)
1.1 Concept and significance of signal equalization
1.2 Signal Compensation Technology
1.3 Balance Coefficient Negotiation
2. Introduction to PCIe Equalization Technology (Electrical Physics)
3. Introduction to PCIe equalization technology (logic physics)
In addition to the blog reproduced in this article, there is another article explaining PCIE balance
Introduction to PCIe5.0 Balance (Complete Edition)_pcie Balance_wqh_Hardware Novice Blog-CSDN Blog
This article is reproduced from the work of MangoPapa in the Alibaba Cloud developer community . The MangoPapa blog is mainly a series of articles on PCIE and UCIe. The blog address has been bookmarked in an article recommended by another blog of mine
1. Introduction to PCIe equalization technology (summary)
1.1 Concept and significance of signal equalization
The signal is sent from the sending end, transmitted through the channel, and reaches the receiving end. During the transmission process, the signal will be distorted, which will affect the correct judgment of the signal at the receiving end. There are many factors that affect the quality of the received signal at the receiving end, such as transmission rate, electromagnetic interference, channel quality, and so on. The more severe the signal distortion, the higher the BER, which affects the communication performance.
In order to obtain a high-quality signal that is easy to judge at the receiving end, the signal can be conditioned and improved at the sending end, during the transmission link, or before the signal is judged at the receiving end, so as to reduce the impact of signal distortion on communication performance. This conditioning of the signal is called signal compensation, or equalization.
Figure 1 is a comparison diagram of signals received by the receiver without equalization and with equalization. It can be seen that after equalization is used, the signal quality has been greatly improved, and it is easier for the receiver to make correct decisions.
▲ Figure 1: The receiving end receives the signal without equalization vs. with equalization
1.2 Signal Compensation Technology
As the transmission rate increases, the skin effect and dielectric loss become more and more serious during signal transmission. In order to recover the transmitted signal correctly at the receiving end, it is necessary to compensate the signal.
Three PCIe signal compensation technologies: Pre-emphasis at the transmitting end, De-emphasis and Equalization at the receiving end. Pre-emphasis and de-emphasis are also called sender equalization. The basic principles of each technology are shown in Figure 2.
▲ Figure 2: Principles of pre-emphasis, de-emphasis, and receiver equalization
The passive transmission line is like a low-pass filter. After the PCIe high-speed serial signal is transmitted from the sending end to the receiving end through the channel, its high-frequency components are attenuated more than the low-frequency components, and the high-frequency components are mainly concentrated on the rising edge of the signal. and falling edge. In order to compensate for this high-frequency attenuation, when the signal is sent, the signal amplitude of the signal jump edge is intentionally enhanced, and the high-frequency component is increased, that is, signal pre-emphasis; compared with the pre-emphasis scheme, de-emphasis is to reduce the jump edge. Outside the signal amplitude, attenuating the low-frequency components can also achieve the goal.
The equalizer at the receiving end is equivalent to a high-pass filter to compensate for the distorted waveform.
1.3 Balance Coefficient Negotiation
At 2.5 GT/s and 5 GT/s, de-emphasis equalization with fixed parameters is only performed at the sending end, and no equalization parameter negotiation is required. After the transmission rate rises to 8 GT/s and above, the equalization of the transceiver end becomes more complicated, and the equalization coefficient needs to be negotiated between the transceiver end to obtain the best transmission performance. The transceiver end negotiates the equalization coefficient in the Recovery.Equalization state of the link training. The whole EQ process includes 4 processes, called 4 Phases. When the rate is 8 GT/s and above, the EQ Phase information is stored in the EC field of TS1 (Symbol 6, bit 0~1).
1.3.1 Phase 0
Phase 0 occurs when the next EQ rate is negotiated but before entering the next rate. During Phase 0, USP returns Preset and Coefficients to DSP. DSP does not have Phase 0.
1.3.2 Phase 1
Both sides of PCIe exchange LF (Low Frequency, symbol 7), FS (Full Swing, Symbol 8), and Post-cursor (Symbol 9) by sending TS1 to each other in Phase 1 to perform rough adjustment of the equalizer to obtain a BER≤10-4 BER performance.
DSP sends TS1 with EC=10b to USP to initiate a jump to Phase 2.
1.3.3 Phase 2
In Phase 2, USP acts as the Master to adjust the Tx coefficient of DSP, which can be divided into Preset adjustment and Coefficient adjustment. The USP independently adjusts the Tx settings of the DSP and its own (USP) Rx settings on each Lane to ensure that the USP can receive the bit stream that meets the requirements (for example, a bit error rate of BER≤10-12 is obtained on each effective Lane ).
DSP recommends its Tx coefficient and its Preset value. In Phase 1, only Preset is used, and in Phase 2, Preset and Tx coefficient are used. After USP receives TS1, it is possible to request a different set of coefficient or preset settings, and then conduct further evaluation until the optimal setting is obtained.
After completing Phase 2, USP sends TS1 with EC=11b to DSP to enter Phase 3.
1.3.4 Phase 3
In Phase 3, DSP acts as the Master to adjust the Tx coefficient of USP. DSP independently adjusts USP Tx settings and its own (DSP) Rx settings on each Lane, and the adjustment method is similar to Phase 2. DSP sends TS1 with EC=00b to mark the end of Phase 3 and EQ.
Among the above four Phases, Phase0/1 uses Preset for coarse adjustment, and Phase2/3 for fine adjustment. If the signal quality requirements are met in the coarse adjustment stage, fine adjustment may not be performed.
Unless specially configured, EQ must be performed at rates above 8 GT/s, at least at the highest rate, and EQ can be skipped at intermediate rates. Of course, you can set bypass_eq during simulation, or set bypass_eq_to_highest_rate, and only perform EQ at the highest rate. For example, the highest support is 32 GT/s, then EQ can be skipped at 8 GT/s and 16 GT/s. When reducing the speed from 32GT/s, it is necessary to re-train the link and do EQ.
Note: In Phase 2 and Phase 3, who is the DSP/USP as the Master to adjust whose Tx? The interpretation of some articles is contrary to this article. Readers please check the official PCIe Spec to judge who is right and who is wrong.
2. Introduction to PCIe Equalization Technology (Electrical Physics)
Link: Introduction to PCIe Equalization Technology (Electrical Physics)
3. Introduction to PCIe equalization technology (logic physics)
Link: Introduction to PCIe Equalization Technology (Logical Physics)
reference
- PCI ExPress Base Spec 5.0, Chapter 4.2.3, Chapter 4.2.6.4.2, Chapter 8.3.3, …
- PCIe Express Technology, Mindshare Inc, Chapter 13
- SNPS PHY databook，chapter 5.11
- Math in a Chip - Equalizer EQ and Its Application to High-Speed External Buses
- pcie equalization study notes
- The concept of dynamic equalization used in PCIE 3.0
- Theory|How to realize the link equalization test of PCIe Gen3/Gen4 receiving end?
- Practice | How to implement PCIe Gen3/Gen4 receiver link equalization test?)
- Equalization Technology in PCIe Electrical PHY(2)-SerDes