A part of the basic knowledge of PCI and PCIe
PCI basic knowledge:
1. The composition of PCI bus: HOST bridge, PCI bridge, PCI device,
2. The role of PCI bridge can isolate PCI devices without affecting the bandwidth of each bus
3. Communication on bus x1 and bus x2 Communication has nothing to do, the devices on the same bus can communicate freely;
4. If there is a problem with the PCI bridge, then the devices under the PCI bridge can communicate freely but cannot send data to the outside.
5. The scalability of PCI refers to PCI A PCI bridge can be mounted on the bus, and then the PCI bridge will launch another PCI bus, and the PCI bridge can be mounted on the PCI bus, and then the PCI bus... (However, the PCI bus takes the HOST host bridge as the root of the tree and connects The device upper limit is 256, including HOST bridge and PCI bridge)
6. The devices on the PCI bus have their own device addresses, and the processor space address and PCI bus address are isolated by the HOST host bridge. (There are many registers in the HOST host bridge, which can make the processor work frequency different from the bus operating frequency. The data is cached through the register. When the processor needs to access the PCI device, it needs to perform address conversion through the HOST host bridge to process The address of the device is converted into a PCI bus address, and then the PCI device can be accessed. Similarly, if the data in the PCI device wants to go outside, the address must be converted through the HOST host bridge. After all, the HOST host bridge is a bridge)
7. One concept: the upstream bus is the bus at one end of the PCI bridge close to the HOST host bridge, and the downstream bus is the other bus at the other end.
8. The address of the PCI device can be dynamically allocated by the system software to resolve address conflicts. (Each PCI device has an independent configuration space, which contains the address of the device on the bus; Note: The configuration space of the PCI bridge has the address range used by its PCI subtree)
9. There are multiple devices on the PCI bus. When they need to communicate, they must apply to the PCI bus arbiter, and they can send data on the bus when they are allowed.
10. Devices on the PCI bus can send interrupt requests to the processor through four interrupt request signals INTA INTB INTC INTD; among them, INTA is a single-function device, and the others are multi-function devices;
11. Devices in the same HOST bridge can communicate ( The HOST host bridge can allow devices in different PCI bus domains to communicate by setting the Inbound register)
12. The HOST host bridge is a special bridge used to isolate the memory domain of the processor from the PCI bus domain and manage the PCI bus domain. The configuration space of all devices in the PCI devices it manages is accessed by the HOST host bridge through the configuration read and write bus cycles.
13. The process of direct data exchange between PCI devices and memory is also called DMA. When PCI bus performs DMA operation, it needs to get the data size and destination address (physical address of PCI bus domain, HOST host bridge will be responsible for address conversion);
14. PCI adopts tree topology structure, each PCI device is equivalent to tree For a node or leaf of the PCI Bus, the algorithm of traversing the tree can be used to traverse the entire PCI Bus. After traversing the tree, the resource requirements of the entire PCI Bus can be obtained, so as to perform uniform allocation.
15. A typical feature of PCI bus operation is to support BURST transmission. What is BURST transmission? First of all, you have to know that the PCI data bus and address bus are multiplexed. This means that on the same bus, a period of time is the address and a period of time is the transmission of data. If there is no BURST transmission, then the address must be sent once before completing a data transmission. This means that the bus is transmitting the address half of the time, which makes the bus and the utilization rate very low. With BURST transmission, you can send a starting address and data length N first, and then you can send data directly after transmitting data 0~N-1, without sending addresses.
16. The first 16 bits represent the domain, the second 8 bits represent a bus number, the third 5 bits represent a device number, and the last 3 bits represent a function number.
17. In the system boot phase, PCI hardware devices remain inactive, but each PCI motherboard is equipped with firmware that can handle PCI. The firmware provides access to the device configuration address space by reading and writing registers in the PCI controller.
18. The first 64 bytes of the configuration address space are standardized. It provides information such as manufacturer number, device number, and version number, which uniquely identifies a PCI device.
19. When the PCI core obtains this array, it will compare each item in the array with the data read from the PCI configuration space to find the correct device for the driver
. 20.
PCIE basic knowledge:
1. PCIE is divided into multiple versions, x1, x2, x4, x8, x16... The transmission rate between all levels has increased by multiples, but the price has also increased by multiples. The PCI-E interface varies according to the bus bit width, including X1, X4, X8 and X16, and the X2 mode will be used for the internal interface instead of the slot mode.
2. The pcie transmission is similar to the network encapsulated into a packet, with a protocol stack.
3. PCIE uses an end-to-end connection, and there can only be one connection between a normal device and a device, but it can be expanded through a pcie bridge.
4. The pcie physical link uses two sets of differential signals.
5. The full name of pcie is: Peripheral Component Interconnect (peripheral component interconnect), which belongs to the local bus, and its main function is to connect peripheral devices
. 6. Important: pcie bus has independent address space, so If the CPU wants to access peripheral devices through pcie, it needs to map the address space of pcie.
7. pcie consists of: RC (root node), siwtch (pcie bridge), end (device)...
8. PCI is a parallel bus; PCI-X is a parallel bus; PCIe is a high-speed differential bus