1. Basic knowledge of PCIE
PCI-E (PCI-Express) is a general-purpose bus specification, which is advocated and promoted by Intel, and its ultimate design purpose is to replace the bus transmission interface inside the existing computer system, which not only includes the display interface, but also includes Various application interfaces such as CPU, PCI, HDD, Network, etc. are provided.
The biggest difference between the PCIe bus and PCI is in the working principle. PCIe is transmitted in a point-to-point serial manner, which is called "serial PCI". Due to the serial transmission method, its operating frequency can reach 2.5Ghz , which greatly increases the transmission rate, and adopts full-duplex communication mode, which doubles the transmission speed. Each PCIe bus device has four data buses when communicating with the outside world, two RX and TX respectively, and two For sending, two for receiving.
The current Intel platform CPU supports a maximum of 40 lanes (lane), but for the current mainstream GPU servers that need to insert multiple high-performance graphics cards, x40 lanes per CPU is not enough. In addition, various data exchanges and synchronizations need to be performed between traditional storage controllers, and PCI-E is generally used, which increases the consumption of the number of channels. For general high-end servers, it is generally configured with two or four channels. The x80 channels are provided under the dual channels. In theory, 10 x8 PCI-E devices can be connected, and some internal embedded PCI-E devices for management and After the channel is occupied, it is easy to connect 8 devices, which can cover almost all application scenarios.
Like most buses, the PCIe bus also includes two parts: electrical properties and protocols. The PCIe specification adopts a layered structure for device design, which consists of a transaction layer, a data link layer, and a physical layer. Each layer is divided into two functional blocks: sending and receiving. At the sending end, the application program (device core A) forms a transaction layer package (TLP—Transaction Layer Package&