[PCIE architecture guide] PCIE summary (1)

What is PCIE

PCIe Peripheral Component Interconnect express
Fast external component interconnection High-speed serial computer expansion bus standard
The local bus of the processor system connects external devices

1. High speed, low latency
2. Support hot swap
3. reliable
4. Good scalability
5. high complexity
6. point-to-point serial connection

Attached is a summary article written by a blogger, which is very good.
"Introduction to PCI Express Architecture" Reading Notes Memory Domain and PCI Bus Domain
PCI Express Architecture Introduction" Reading Notes HOST Main Bridge of X86 Processor
In Intel's x86 processor system, all external devices use PCI bus management.

Device ID: The specific device Vendor ID produced by the manufacturer represents the manufacturer
Revision IDregister of the PCI device to record the version number of the PCI device. The Class Code register records the classification
Cache Line Sizeregister of the PCI device.
Use Subsystem IDand Subsystem Vendor IDto distinguish devices

Some PCI devices need to complete basic initialization settings before the processor runs the OS.

PCIe devices use INTxinterrupt messages to simulate the interrupt signals of PCI devices.
Use pci_resource_startthe function to obtain the physical address of the memory domain corresponding to the BAR space, but the address read from the BAR register cannot be used.



DFS algorithm depth-first traversal of PCI tree

Access to configuration registers of PCI devices must haveBus Number 、Device Number 、Function Number和Regiseter Number

Negative decoding PCI-to-ISA bridge can be used as a negative decoding device when there is no response from any PCI device.

Memory write usage Postedmode, memory read usage Non-Postedmode

PCEI link

RC（Root Complex）The main function is similar to the HOST main bridge in the PCI bus, but many functions have been added.
Intel uses RC to manage the PCIe bus, which not only manages the data access of PCIe devices, but also includes a series of content such as access control, error handling and virtualization technology.
The high-speed differential bus has a higher clock frequency and fewer signal lines for end-to-end connection .

LaneTwo sets of differential signals in the data path, a total of 4 signal lines .

switch

Switch can adopt Crosslinkconnection mode. Using a non-transparent bridge only solves the data path problem between two processors, and the final solution is to use MR-IOV technology. Requirement: The Switch has multiple upstream ports interconnected with different RCs.

Devices based on the PCIe bus, also known as EP(Endpoint).

Three VC arbitration methods, namely
Strict Priorityabsolute priority and
RR（Round Robin）round robin
WRR（Weighted Round Robin）weighted round robin algorithm.