PMCR（Power Management Capabilities Register）and PMCSR（Power Management Control and Status Register)
PMCR registers consist of 16 bits, where all bits and fields are read-only. The main purpose of this register is to record the physical attributes of the current PCIe device. The system software needs to obtain the information of the current PCIe device from the PCR register before modifying the PMCSR register.
DWRR (Deficit Weighted Round Robin) and WRR (Weighted Round
Robin) are two common scheduling algorithms for traffic scheduling and fair sharing of bandwidth in network switches or routers.WRR algorithm:
It is a weight-based round-robin scheduling algorithm. Each traffic flow is assigned a weight value, and the traffic flow with higher weight value will get more bandwidth share. The scheduler allocates bandwidth in proportion to the weight value, and each traffic flow sends a certain number of packets in turn. When all traffic streams have been sent for a round, the scheduler restarts the allocation for the next round.DWRR algorithm:
It is improved on the basis of WRR algorithm and introduces the concept of "deficit". Each traffic flow is assigned a weight value and a gap value. The scheduler allocates bandwidth in proportion to the weight value and keeps track of the shortfall value for each traffic flow. In each time slice, the scheduler will send packets for each traffic flow, but if a flow is not short enough to send a full packet, it will wait for the next time slice. This ensures that high-weight traffic streams send more packets in the same time slice, thereby sharing bandwidth more fairly.
The DWRR algorithm allows the scheduler to dynamically adjust the sending frequency of each traffic flow by introducing a gap value, so as to better adapt to traffic changes. Compared with the WRR algorithm, the DWRR algorithm can provide better traffic fairness and bandwidth utilization.It should be noted that the DWRR and WRR algorithms are usually used for traffic scheduling of network devices, rather than scheduling at the application level. In practical applications, specific implementations and parameter settings may vary to suit specific network environments and requirements.
MCH=Virtual PCI devices with high bandwidth requirements on the north bridge
ICH=South bridge integrates some low-speed PCIe ports and low-speed external devices, such as PCI-to-USB bridges, LPC bus
controllers .
flow control
Rated-BasedThe mechanism is suitable for the data transmission mode of "predictable bandwidth"
Credit-Basedand the mechanism is more suitable for "burst data transmission".
In the PCIe bus, the PCIe device must support MSIor MSI-Xinterrupt request mechanism, and may not support INTxinterrupt messages.
Sequence of the PCIe bus
Producer/consumer model concurrent collaboration model
PCIe bus order support Relaxed orderingmode for data transfer.
ID-Base Ordering
IDO model "data flow" TLPs sent from the same data source belong to the same "data flow", and TLPs sent from different data sources belong to different "data flows".
HOL（Head-of-Line）Blocking. The Ingress port can only process one packet at a time.
VOQ（Virthal Output Queue）Ingress ports provide separate send buffers for each egress port.