Table of contents
overview
The initialization process of the PCIe link is relatively complicated. When the PCIe bus performs link training, the physical layer of the PCIe device will be initialized, and the receiving module and related link status information will be sent. When the link training is successfully completed, the devices at both ends of the PCIe link will Communication is possible.
Link training is mainly done by hardware logic without the participation of system software. In addition, when the PCIe device returns to the normal working mode from the low power consumption state, or when an error occurs in the PCIe, it also needs to be reconnected.
Purpose of link training
It is mainly to carry out the PCie physical layer, port configuration information, corresponding link status, and understand the topology structure of the opposite end of the link, so that the devices at both ends of the PCIe link can communicate.
a few key concepts
Lane reveral ：
The lanes used by the devices at both ends of the PCIe link can be connected out of order
Polarity inversion：
On a single lane, the polarity of the differential can also be connected in a wrong order
De-skew:
The PCI bus can use multiple lanes for data exchange, and the delays of data packets passing through different lanes are not exactly the same. When the PCIe bus is trained, it is necessary to deal with the delay differences of these different lanes and make compensation
link number：
There are multiple downstreams in a switch, and they are numbered using 0~n. These numbers are stored in the hardware logic of the switch and are no longer in the configuration space.
Lane number：
Divided into two categories, one is the physical lane number (before link training) and the other is the logical lane number (after link training), which should allow PCIE to allow out-of-sequence connections. Therefore, the logical lane and the physical lane are not necessarily the same , so when the bus link is trained, it is necessary to initialize the link of rc or sw.
Bit lock：
When the pcie bus transmits data, clock synchronization is required, but the pcie link does not have this clock signal, so when performing bus training, the receiving end needs to extract the receiving clock from the data message at the sending end. This process is called bit lock
Symbol lock：
During link training, the PCIe link needs to confirm the COM character first. 11000001010, 00111110101
Several special sequences:
TS1 and TS2:
TS1 mainly detects the link configuration information of PCIe, and ts2 confirms the detection result of TS1 sequence;
(It’s just that the characters from 6th to 15th have different meanings)
0: COM control character, indicating the beginning of the ts1 and ts2 sequence, the character sequence will reset the LF-SR sequence.
1: In the initialization phase of the link, the first character is placed pad, which is empty; while in the link configuration phase, the character is placed
The link number of the port.
2: In the link training phase, the first character is used to place the pad, which means it is empty, and in the link configuration phase, this character is used to place the lane number of the port;
3: The number of FTS, the unreasonable PCIe link needs to use the unreasonable FTS sequence, so that the PLL at the receiving end can lock the receiving clock.
4: Store the data rate supported by the current PCie device.
5: Store command, the first digit is hot reset; the second digit: loopback; the third digit: disable scrambling; the fourth digit is: compliance receive. When the acceptance logic receives the TS1/TS2 sequence, it will perform corresponding operations according to the character.
IDLE；
Under normal circumstances, when the sending end enters the electrical idle state, an eios sequence must be performed to the opposite end.
FTS：
A single FTS sequence consists of one com and three FTSs, the main purpose of this sequence is to enable the acceptance logic to regain the bit/symbol lock;
Skip：
It consists of a com and three skip and characters. The main purpose is to perform clock compensation. The clock of PCIe is 2.5G+-300ppm, of which 300ppm means. One million clocks, there will be 300 offsets. If the PCIE does not use the skip sequence, the local clock and the extraction from the message may fluctuate, which may cause data transmission failure.
In the receiving logic of the PCIe device, two clocks are used, one clock is recovered from the PLL message, and the other is the local clock. In the bus, use the elastic buffer technology to process the frequency difference and phase difference between the two clocks. The elastic buffer consists of a buff. One end of the FIFO uses the local clock domain, and the other end uses the recovered clock domain. Due to the clock mismatch, there will be overrun and underrun. The bus stipulates that after characters 1190-1538, a skip sequence must be sent for compensation.
LTSSM state machine
LTSSM is a relatively important state machine in link training.
When doing bus link training, the LTSSM state machine will be used. It consists of 11 states in total, as shown in the figure below.
Each state:
Detect state:
Introduction: When the PCIe link is reset or the data link layer fills in some registers, ltssm will enter this state, which is also the initial state of LTSSM. When the PCIe link is in this state, the sending logic TX does not know the right The end accepts the existence of logic RX, so use the Receive Detect identification logic to judge whether the peer accepts logic RX can work normally, and then enter other states.
Details: detect is composed of detect.quiet/detect.active two sub-state groups. When the PCIe device enters reset, it first enters the quiet state. Logic power consumption is the lowest), when the PCIe device is in the quiet state, the default rate is 2.5G, when 12ms passes or any lane exits idle, PCIe enters the active stage,
Polling：
When the PCie link enters this stage, it will send ts1 and ts2 to the peer and accept ts1 and ts2 from the peer
To determine the polarity of bit/symbol and lane, in this state, a loop test will be performed to confirm that the current pcie can work normally.
Cfg：
When entering this state, it will determine the width of the link, link number, lane reveral/porarity inverion, delay of lane to lane, the most important state of the ltssm state machine in this state, and it is worth noting that it is in the cfg state. Use 2.5g uniformly until you enter the l0 state.
L0 state: PCie is in normal working state.