1. Egress and Ingress
In the Switch, the port through which the data flows out is called the Egress port, and the Ingress refers to the port through which the data flows into the Switch.
2.DSP（Down Stream Port）和USP（Upper Stream Port）
For each functional device, the ports used to connect upstream and downstream devices are collectively called DSP or USP (the illustration in the figure below).
In a PCIe system, the upstream port and downstream port are fixed, but the Ingress port and Egress port are not fixed, and are related to the transmission direction of the data packet.
3. Traffic category (TC)
The TC is a TLP header field sent within the packet, unchanged as it passes through the structure end-to-end. Local application software and system software should determine what TC flag a certain TLP uses based on performance requirements. The TC field is a 3-bit long field, which can divide different traffic into 8 traffic categories (TC0~TC7). The device must implement VCO. The device or switch needs to realize the TC-VC mapping logic, and forward the TLP with a given TC number through the link using the buffer of a specific VC number. PCIe has the ability to map multiple TCs to one VC, thus reducing device cost by providing support for a limited number of VC buffers.
4.VC: virtual channel
VCs are physical buffers that provide a means of supporting multiple independent logical data streams over a physical link through the use of transmit and receiver virtual channel buffers. A PCIe device can implement up to 8 VC buffers (VC0~VC7). The value of the Extended VCCount field is the number of VCs supported except VC0. When it is 0, it means that only VC0 is supported; when it is 1-7, it means that it supports 1-7 additional VCs.
5. Phase:
Each entry in the VC arbitration table represents a phase. The specification defines three WRR configurations, with 128, 64, and 32 entries respectively. The number of arbitration entries supported by a specific device is reported by the VCArbitrationCapability field in the port VC capability register 2, and the size of the table is selected by writing the value of the VC ArbitrationSelect field in the port VC control register (see the figure below).
8. LBC, DBI, ELBI and CDM
LBC（Local Bus Controller）：
The LBC module of EP provides a mechanism for peer USP or local CPU to access CDM internal registers and ELBI external application registers through DBI.
DBI（data bus interface）:
It is an interface defined by synopsys to access PCIe registers. The PCIe protocol specifies two configuration spaces: PCI Configuration Space and PCIe Extend configuration Space. And often IP generators will add a configuration space of their own, and the configuration space added by synopsys is: Port logic Synosys Register.
As shown in the figure below, the CPU on the EP side can access the CDM internal registers of the PCIe Controller through the DBI interface, and can also access the ELBI external application registers.
ELBI（External Local Bus Interface）:
Forward the inbound register read and write request received by the PCIe Controller to the external application register.
CDM (Configuration-Dependent Module): includes the standard PCIe configuration space and the register space (port logic register) specified by the PCIe Controller.
9. Abbreviations & definitions of modules involved in PCLE and VIP:
PMC： Power Management Controller
LBC ： Local Bus Controller
DBI ： Data Bus Interface
MSG_GEN： MessageGeneration Module
HOT PLUG：Hot Plug ControlModule
RBYP: Receive Bypass Interface
TRGT1: Receive Request Interface
ELBI: External Local Bus Interface
MSI: Message Signaled Interrupt (MSI) Interface,
MSI-X Interface, the interrupt mode selected in DPDK, uses this interface.
XALI 0/1/2 : Transmit Interfaces 0/1/2
VMI : Vendor Message Interface
SII : System Information Interface
10.PCIE controller和PCIE PHY：
The PIPE interface is used to connect the PCIE controller and the PCIE PHY. The controller uses the PIPE interface to send the parallel number to the PHY for operations such as parallel-to-serial conversion. The PHY sends the parallel number obtained through the serial-to-parallel conversion to the controller through the PIPE interface.