Introduction
We know that the interrupt mechanism brings many advantages, such as real-time response, saving CPU resources, multi-task support, etc. Interrupts enable the system to interact and collaborate with external devices efficiently.
There are three interrupt modes in PCIe, namely INTx, MSI, and MSI-X. The three interrupt types will be described below.
YOU
INTx is generally called a traditional (lagacy) interrupt. It has four lines, which report interrupts through INTA, INTB, INTC, and INTD. A simple example is shown in the figure below:< a i=1> Most PCI devices only use the INTA signal, rarely use the INTB and INTC signals, and the INTD signal is rarely used. In the PCI bus, the Interrupt Pin register of the PCI device configuration space records which INTx signal the device uses. A simple PCI bus INTx interrupt processing flow is as follows: 1. The PCI device generates an interrupt request through the INTx sideband signal and passes through the Interrupt Controller. PIC), it is converted into an INTR signal and sent directly to the CPU; 2. After the CPU receives the INTR signal set, it is aware of the occurrence of the interrupt request, but does not know what it is at this time Interrupt request. Therefore, a special instruction is used to query the interrupt request information. This process is generally called Interrupt Acknowledge. 3. After this special instruction is sent to the PIC, the PIC will return an 8-bit interrupt vector (Interrupt Vector) value to the CPU. The interrupt vector value corresponds to the INTR request sent; 4. After the CPU receives the interrupt vector value from the PIC, it will search in the Interrupt Table in its Memory. The corresponding interrupt service routine (Interrupt Service Routines, ISR) is located in Memory; 5. Then the CPU reads the ISR program and processes the interrupt.
MSI
MSI (Message Signaled Interrupt) Compared with traditional interrupt methods, MSI provides higher flexibility and performance, and has the following advantages:
1. The device transfers data to the memory Write data and then initiate a pin interrupt. It is possible that when the CPU receives the interrupt, the data has not yet reached the memory. When using MSI interrupts, the write that generates the interrupt cannot exceed the write of data (the transaction order rule of PCIE/PCI can guarantee this), and the driver can be sure that all data has reached the memory.
2. Traditional pin-based interrupts will be shared by multiple devices. When interrupts are shared, if an interrupt is triggered, the corresponding interrupt processing functions need to be called one by one in Linux, which will improve performance. loss, while MSI does not have the problem of sharing.
3. For multi-functional PCI devices, each function has at most one interrupt pin. When a specific event occurs, the driver needs to query the device to know which event occurred, which will reduce the number of interrupts. processing speed. A device can support 32 MSI interrupts, and each interrupt can correspond to a specific function.
Both MSI and MSI-X interrupts report interrupts through the write request TLP to write Message Data to the Message Address in the MSI/MSI-X Capability structure. It can be simply understood as writing the value Message Data to the Message Address. This An interrupt will be triggered. It should be noted that the Message here is not the Message type of Tlp. MSI is essentially a Memory Write. Message Address and Message Data depend on the processor architecture. The structures of MSI are as follows:
Capability ID: identifies the current Capability type, 05h represents the MSI function, and others can refer to the PCI capability explained in the configuration space.
Next Capability Pointer: The offset address of the next Capability Structure. If its value is 00h, it means reaching the end of the Linked List.
Message Control Register: MSI format and supported functions and other information, as shown in the figure below:
The specific description of this register is as follows: < a i=5> Message Address Register: The address that needs to be written to generate an MSI interrupt. It can be seen that 1:0 must be 0. Message Data Register: The content that needs to be written to generate an MSI interrupt. It can be seen that no matter which structure is used, the length of Message Data is 16 bits. Here, the Message Address Register and Message Data Register are configured by the Host-side driver to the PCIe device-side registers. When the PCIe device needs to generate an interrupt, it will generate a Memory Write type TLP packet, copy the Message Address Register and Message Data Register to the corresponding fields of the TLP, and then send it to the RC. The RC receives the TLP packet and parses it, and then passes The ITS module generates an LPI interrupt, and finally the CPU can trigger the corresponding interrupt. (I just mentioned it briefly here. For more details, you can look at the Gic-related information. The Gic version used by the armv8 architecture is generally Gic_v3 or Gic_v4) The rules for generating MSI TLP are as follows: No Snoop and the value of Relaxed Ordering bits must be 0 The TLP length value must be 01h First BE must be 1111b Last BE must 0000b Mask Bits: After masking the relevant interrupt vector (Interrupt Vector), the MSI will not be sent. Software can enable or disable the sending of certain MSIs in this way. Pending Bits: If the relevant interrupt vector is not masked and a relevant interrupt request occurs, the corresponding bit in the Pending Bits will be set. Once the interrupt message is sent, this bit will be cleared immediately.
MSI-X
The basic principles of the MSI and MSI-X mechanisms are the same. The MSI interrupt mechanism can only support up to 32 interrupt requests and requires continuous interrupt vectors, while the MSI-X interrupt mechanism can support more interrupt requests and does not require continuous interrupt vectors. , this is also the most important point. MSI-X was proposed in PCIe3.0, and the MSI-X mechanism has made some upgrades and improvements to MSI.
The structure of MSI-X Capability is as follows:
Capability ID: The ID number of the Capability structure, its value is 0x11.
Message Control: Stores the status and control information of the current PCIe device's interrupt request using the MSI-x mechanism, as shown below:
Table BIR: BAR Indicator Register. This field stores the location of the MSI-X Table. The PCIe bus specification stipulates that the MSI-X Table is stored in the BAR space of the device. This field indicates which BAR space in the BAR0 ~ 5 registers the device uses to store the MSI-X table.
Table Offset: Stores the offset of the MSI-X Table in the corresponding BAR space.
PBA (Pending Bit Array) BIR: In which BAR space of the PCIe device the Pending Table is stored. Under normal circumstances, the Pending Table and MSI-X Table are stored in the same BAR space of the PCIe device.
PBA Offset: This field stores the offset of the Pending Table in the corresponding BAR space.
Summarize
PCIe has three interrupts, namely INTx interrupt, MSI interrupt, and MSI-X interrupt. In the PCI bus, all devices that need to submit interrupt requests must be able to submit interrupt requests through the INTx pin, and the MSI mechanism is An optional mechanism. In the PCIe bus, the PCIe device must support the MSI or MSI-X interrupt request mechanism, and does not need to support the INTx interrupt message. However, for a specific PCIe device, only one type of message may be supported.
Whether it is MSI or MSI-X, they are essentially based on Memory Write. Compared with MSI, the main upgrade of MSI-X is that interrupts can be discontinuous.