Makefile contains the target file, dependent files, run the command three parts.
The basic format of each part, for example, the following:
test: prog.o code.o
gcc -a test prog.o code.o
Them, test the first line is the target file . prog.o, code.o is dependent files ;
Gcc -o test prog.o code.o second line is to run the command .
Throughout the Makefile is such a format.
Reference links:
https://blog.csdn.net/haoel/article/details/2886
Makefile pseudo-objective:
https://www.cnblogs.com/hnrainll/archive/2011/04/12/2014082.html