do file explanation
Questasim do file explanation
do file
The # beginning is comments. I’m not sure if written in the do file will be treated as a comment; if it doesn’t work, remove the
DO file, which is essentially a Tcl script. Can contain many Tcl structures, such as programs, conditional operators, math and trigonometric functions, regular expressions, etc.
Parameters of vsim
- The parameter "-novopt" prohibits optimization (no vopt), which may cause some unimportant signals to be automatically ignored by modelsim because of vopt, and this parameter is generally retained;
- The parameter "-c" means to enter the command line mode, if there is no such parameter, it means to enter the GUI mode.
- The parameter "-L altera_ver" is to add the simulation library, where the logical library name is used directly, or the physical library name and path can be used as follows; if the library and source files are compiled into the work library, this is not required parameter;
- -l lowercase L, output log file vsim -l sim.log
- -wlf saves the simulation result as a WLF file. The simulation results can be viewed in the GUI during debugging.
- At the system prompt, enter vsim –view counter.wlf.
- + UVM_TESTNAME = my_case0
+ UVM_NO_RELNOTES
+ UVM_TIMEOUT = 100000000
if [file exists "work"] {
vdel -all} #有work这个目录 则删除
vlib work #vlib work ---- 在工作目录下建立一个work目录
#vcom 编译vhd；如果是verilog 则使用vlog
vcom -f dut.f
vlog -f tb.f
vopt top -o top_optimized +acc +cover=sbfec+tinyalu(rtl).
vsim top_optimized -coverage +UVM_TESTNAME=random_test
set NoQuitOnFinish 1
onbreak {
resume}
log /* -r
run -all
coverage exclude -src ../../tinyalu_dut/single_cycle_add_and_xor.vhd -line 49 -code s
coverage exclude -src ../../tinyalu_dut/single_cycle_add_and_xor.vhd -scope /top/DUT/add_and_xor -line 49 -code b
coverage save random_test.ucdb
vsim top_optimized -coverage +UVM_TESTNAME=add_test
set NoQuitOnFinish 1
onbreak {
resume}
log /* -r
run -all
coverage exclude -src ../../tinyalu_dut/single_cycle_add_and_xor.vhd -line 49 -code s
coverage exclude -src ../../tinyalu_dut/single_cycle_add_and_xor.vhd -scope /top/DUT/add_and_xor -line 49 -code b
coverage save add_test.ucdb
vcover merge tinyalu.ucdb random_test.ucdb add_test.ucdb
vcover report tinyalu.ucdb -cvg -details
quit
#vcom 编译vhd；如果是verilog 则使用vlog
dut.f #Designed file path
tinyalu_dut/single_cycle_add_and_xor.vhd
tinyalu_dut/three_cycle_mult.vhd
tinyalu_dut/tinyalu.vhd
tb.f #simulated file path
+incdir+ #means include dir contains a directory to come in
tinyalu_pkg.sv
tinyalu_bfm.sv
top.sv
+incdir+tb_classes
wave.do
In the wave window ctrl+s
/home/enrsuwg/rst_uvc/rst_agent/wave.do
makefile
Makefile is another form of alternative to do, which may be more convenient;
just write a file name and ask Makefile, the content is as follows.
Under linux, you can test on the terminal to see if the vsim command
is recognized. If recognized, you can run directly with make; add -c to not start gui
all: create_lib compile simulate
create_lib:
vlib work
compile:
vlog -timescale "10ps/10ps" -l comp.log -sv ../test_pkg.sv param_pkg.sv rst_agent_pkg.sv dut.sv top_tb.sv
simulate:
vsim -l sim.log -c top_tb -novopt -do "run 10000ns" +UVM_TESTNAME=my_case0
#run -all
#+UVM_TESTNAME=my_case0
clean:
rm -rf work