Write a makefile to compile *.c and link to executable target

https://wenku.baidu.com/view/b1ec946027d3240c8447ef9a.html

GNU+make Chinese Manual V3.8

<=========From Docs==============>

Generally, we can use "$(wildcard *.c)" to get a list of all .c files in the working directory.
More complicated
function to get the list of .c files in the working directory; The filename suffix .c is replaced with .o. This way
we can get a list of .o files that can be generated in the current directory. Therefore, in a directory, you can use the
following Makefile to compile all .c files in the working directory and finally link them into an executable
file:
#sample Makefile
objects := $(patsubst %.c,%. o,$(wildcard *.c))
foo : $(objects)
cc -o foo $(objects)
Here we use make's implicit rules to compile .c source files. Assignments to variables also use a
special symbol (:=). For variable definitions, please refer to Section 6.2 Two Types of Variable Definitions. For the function "patsubst", please
refer to Section 8.2 Text Processing Functions

 

<--------------My Example ------>

#Settings for Ubuntu
CC=arm-none-eabi-gcc
LINK=arm-none-eabi-ar
TARGET=libSample-linaro.a
CCFLAG=-Dxxx=1 -DHHH  -I ./

#Start Test!

allobjects := $(patsubst %.c,%.o,$(wildcard *.c))
$(TARGET): $(allobjects)
    $(LINK) rcs $(TARGET) $(allobjects)

$(allobjects): %.o:%.c
    $(CC) $(CCFLAG) -o $@ -c $<

clear:  
    rm -rf $(TARGET)
    rm -rf $(allobjects)

#end Test