Make and Makefile learning one of Makefile file writing rules
1. Basic use
test $ ls -l
总用量 20
drwxrwxr-x 2 hww-arm hww-arm 4096 9月 12 13:14 file
drwxrwxr-x 2 hww-arm hww-arm 4096 9月 12 13:14 hello
drwxrwxr-x 2 hww-arm hww-arm 4096 9月 12 11:03 include
-rw-rw-r-- 1 hww-arm hww-arm 558 9月 12 11:02 main.c
-rw-rw-r-- 1 hww-arm hww-arm 339 9月 12 13:26 Makefile
test $ vim Makefile
#以下为Makefile文件内容
#/*以下为常用模板，用于Makefile信息*/
VERSION = 1
PATCHLEVEL = 0
SUBLEVEL = 0
EXTRAVERSION =
NAME = TEST
CC =gcc #变量CC定义编译器,关于变量说明， 见附A.1
FLAGS = #变量FLAGS为编译器参数
LD = #变量LD为编译器的链接，如使用到线程时，需要定义变量LD = lpthread
vpath %.c ./hello/ #见附B.1
vpath %.c ./file/
MYOBJ_o = main.o file.o hello.o #变量MYOBJ_o，用于保存所有的依赖文件*.o
myobj : $(MYOBJ_o) #见附C.1
$(CC) -o myobj $(MYOBJ_o)
main.o : main.c
$(CC) -c main.c
file.o : file.c #见附D.1
hello.o : hello.c
clean :
-rm -f *.o myobj
.PHONY:clean #见附E.1
#/* Makefile end */
test $ make
gcc -c main.c
gcc -c -o hello.o ./hello/hello.c
gcc -c -o file.o ./file/file.c
gcc -o myobj main.o hello.o file.o
Appendix A.1 Explanation of variables
1. In the Makefile file, the variable name can be customized, and it can generally express its meaning. In the Linux kernel, the following variables are generally used to express the kernel version information in the first few lines:
VERSION =
PATCHLEVEL =
SUBLEVEL =
EXTRAVERSION =
NAME =
The above ordinary variables are similar to macros in C language. In C language, the way of using variables is different from macros in C language. The way of using variables in Makefile:
$(VERSION)
2. Variables in variables: '=' , ':=', '?=', '+='
2.1 = Operator
1, = The left side is a variable, the right side is the value of the variable, but this value can also be a variable;
2, = The value on the right side is not necessarily It is already defined and can be defined in subsequent lines, that is, the following methods are supported:
NAME = $(FIRST) $(LAST)
FIRST = Zhang
LAST = San
3. Example:
#/*vim Makefile start */
NAME = $(FIRST) $(LAST)
FIRST = Zhang
LAST = San
all:
echo $(NAME)
.PHONY:all
#/* end*/
test $ make
echo Zhang San
Zhang San
2.2 := 操作符
:=操作符和=操作符不同之处在于，使用 := 右侧的变量前，变量必须赋值，否则认为主空，
例：
#/*vim Makefile start */
NAME := $(FIRST) $(LAST)
FIRST = Zhang
LAST = San
all:
echo $(NAME)
.PHONY:all
#/* end*/
test $ make
echo
2.3 ?= 操作符
?=操作符和=操作符不同之处在于，如果事先变量被赋值，此次将不再被赋值，如果没有赋值，将被赋值
例：
#/*vim Makefile start */
NAME = Li Si
NAME ?= $(FIRST) $(LAST)
NAME2 ?= $(FIRST) $(LAST)
FIRST = Zhang
LAST = San
all:
echo $(NAME)
echo $(NAME2)
.PHONY:all
#/* end*/
test $ make
echo Li Si
Li Si
echo Zhang San
Zhang San
2.4 += 操作符
+=操作符功能：如果变量事先定义了值，现在需要进行增加值，此时可以使用
例：
#/*vim Makefile start */
NAME = Li Si
NAME += $(FIRST) $(LAST)
FIRST = Zhang
LAST = San
all:
echo $(NAME)
.PHONY:all
#/* end*/
test $ make
echo Li Si Zhang San
Li Si Zhang San
Attached B.1 vpath keyword usage
How to use the vpath keyword:
vpath <pattern> <dir> //在dir目录中搜索pattern规则的文件如：%.c文件 、%.o文件 、.h文件等
vpath <pattern> //删除某个搜索规则，如不搜索.h文件
vpath //取消所有的搜索，只搜索当前目录
一般可用于配合隐匿规则使用
Appendix C.1 Use format
1. In the Makefile file, there are two expressions for using the target file:
Method 1:
targets(即目标文件) : prerequistites(即依赖文件）
command1（即生成目标文件需要执行的命令）
command2
............
Way two:
targets(即目标文件) : prerequistites(即依赖文件）；command1
command2
............
Attach D.1 implicit rules
make工具会自动使用gcc -c 命令，将一个扩展名为.c的源文件编译成一个同名的.o的目标文件，
因此，当编译一个单独的.c文件到.o文件时，可以使用隐含的规则，让make工具自己推导
此案例中，使用vpath关键字和隐式规则配合使用。
Attach E.1 pseudo target
1. False target format:
伪目标 ：
command
.PHONY 伪目标
2. Use
make 伪目标
3, example
test $ make clean
According to the example, after executing the make clean command, the execution command will be executed:
-rm *.o myobj
This command has one more symbol'-' than the shell, its function is to ignore the command execution error and continue to execute downward, that is, if there is no .o file, the myobj file will be deleted, and vice versa.
The command method with the same function as the above command is as follows:
clean :
rm *.o myobj
.IGNORE:clean
#//同样声明clean为伪目标，并且忽略命令执行过程中的错误