Makefile knowledge

1. Makefile syntax

                           Generated files (targets): dependent files (the Prerequisites)

                                                How to file generation (recipe)

test.o : a.o,b.o,c.o
            gcc -o a.o b.o c.o

a.o: a.c
      gcc -c a.o a.c

b.o: b.c
       gcc -c b.o b.c

c.o: c.c
      gcc -c c.o c.c

Wherein when the preceding code empty spaces but not Tab

 

2. But this looks like too much trouble if there are a lot of files and write very long so in this case we need some clothes to represent all common file

test：a.o b.o
        gcc -o test a.o b.o

%.o: %.c
    gcc -c -o $@ $<

Where $ @ represents the target file (, o file)

$ <Represents the first dependent files (.c file first)

If you use the $ ^ means that all dependent files

test：$^
        gcc -o test a.o b.o

%.o: %.c
    gcc -c -o $@ $<

.PHONY This is for when there are other files can not be called a clean execution of documents you need to add it

 

3. Immediately variables:

                 A  ：= abc 

4. Variable delay: only when in use it will be the last assignment only have value

    A = $（C）

   C= 124

  C= 123

   A case 123

5. append Plus + = not overwrite the original value would increase after the new value

   

6. The use of the function:

     A = a b c

     B = $(foreach f, $(A)， $(f).o)

all:

       @echo B = $(B)

A variable inside the called each name is abc de .o file into forms of

    

$(filter patent, text)

Select a value in line with the format string patent

 

 

$(filter-out patent, text)

Patent does not meet the selection value in string format

 Note that patent to add%

 

$(wildcard patent)

It is real like that kind of file format patent

 

$(patsubst patent replacement text)

Replace the patent text to replacement. .