C language makefile file

Source file in software engineering are many, according to its type, function modules were placed in a number of directories and files, which files need to compile those documents compiled, those files need to be recompiled, even more complex functional operation, which means our system has been compiled.

In linux and unix, there is a powerful utility called make, you can use it to manage multi-module program to compile and link until the executable file.

make program needs to compile a rule description file called makefile, makefile document describes the dependencies between compilation rules the entire software engineering and individual files.

makefile are like a shell script that can execute operating system commands, its benefits is that we can achieve "Automation compilation", once written, as long as a command to make the whole software functions completely automatically compiled and improve the efficiency of software development.

make is a command tool, the tool is a command in the makefile instructions explain, in general, most compilers have this command, you can make use of a number of re-compiled minimized.

First, write the makefile

The makefile rule can be very complex, more complex than a C program, let me introduce its simple usage by example.

File name: makefile, as follows:

all:book1 book46 

book1:book1.c
        gcc -o book1 book1.c

book46:book46.c _public.h _public.c
        gcc -o book46 book46.c _public.c

clean:
        rm -f book1 book46

first row

all:book book46

all: This is a fixed wording.

book1 book46 expressed the need to compile a list of the target program, in the middle separated by spaces, if the list is very long, you can use \ newline.

second line

Blank lines in the makefile as a C program, empty line, just to write neatly, does not make sense.

The third row

book1:book1.c

book1: represents the goal of the program needs to be compiled.

If you are compiling a target program book1, need to rely on the source book1.c, when book1.c content has changed, it will make the implementation of recompiling book1.

Fourth row

 gcc -o book1 book1.c

This is a compile command, and command the operating system command line input of the same, but pay attention to a problem before gcc use the tab key, looks like eight spaces, not actual, must use tab, not spaces.

Sixth line

book46:book46.c _public.h _public.c

The same as the meaning of the third row.

book46: represents the compiled object program.

If you are compiling a target program book46, need to rely on the source book46.c, _public.h and _public.c three documents, as long as any of the contents of a change, do make time will be recompiled book46.

Seventh row

gcc -o book46 book46.c _public.c

The same as the meaning of the fourth row.

Ninth row

clean:

Clear the target file, remove the commands executed by the script after the tenth line.

Tenth row

 rm  -f  book1 book46

Clear script commands target file, pay attention, before rm is a tab key, not spaces.

Two, make command

makefile ready, at the command prompt execution can make the makefile to compile all parameters specified target file.

Make the program compiled object program.

Perform another make.

Because all of the target program are up to date, so there is no target can be compiled tips.

Execute make clean, clear instruction execution target file.

Then execute make recompilation.

_Public.c modify the program, just change something, as long as the change on the line.

Then make

Note that, because book46 rely on one source _public.c changed, so book46 recompiled.

book1 without recompiling, because book1 dependent source file has not changed.

Three, makefile variables in the file

makefile, the variable is the value of a name is a text string, variable. Target in the makefile, depending when the reference variable, the variable will be replaced by its value command or elsewhere.

Let me introduce its simple usage by example.

CC=gcc
FLAG=-g

all:book1 book46

book1:book1.c
        $(CC) $(FLAG) -o book1 book1.c

book46:book46.c _public.h _public.c
        $(CC) $(FLAG) -o book46 book46.c _public.c

clean:
        rm -f book1 book46

first row

CC=gcc

Define the variable CC, assignment gcc.

second line

FLAG=-g

Define the variable FLAG, assignment -g.

Seventh row

  $(CC)  $(FLAG) -o book1 book1.c

$ (CC) and $ (FLAG) is to use the value of the variable CC and FLAG, similar to the C language macro definition, the result of substitution is:

In a makefile, the benefits of using two variables: 1) If the instruction uses many compile variable, as long as the value of the variable is modified, all equivalent modifications compiler directives; 2) the relatively long, common compiler directives using variables to represent, let makefile more concise.

Fourth, the application experience

Write the makefile can be very complex, complicated I do not want to see in the actual development, we do not need so complex makefile, I seek simple and practical way, freeing up more time and energy to do more important things, those who the makefile written very sophisticated programmers in my opinion is enough support.

Five, Homework

You put all this time to write a program to write the makefile, never again to use the gcc at the command prompt.

Sixth, Copyright

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Source: C Language Technology Network (www.freecplus.net)
Author: Ethics code Agriculture

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