20180411 Makefile study notes - introduction to makefile (rules of makefile)
Perceptual understanding of makefile: When the
make command is executed, a makefile is required to tell the make command how to compile and link the program;
eg: there are 8 C files and 3 header files in the project, we need to write a Makefile to tell make Command how to compile and link these files, our rules are:
(1) If the project has not been compiled, then all our C files must be compiled and linked.
(2) If some C files of this project are modified, then we only compile the modified C files and link the target program.
(3) If the header file of this project has been changed, then we need to compile the C file that references these header files and link the target program.
As long as our Makefile is well written, all of this can be done with just one make command.
First, the rules
of makefile The following are the rough rules of makefile:
target...: prerequisites...
command
...
...
target is the target file, which can be an Object File, an executable file, or a label ( Label), the feature of label will be described in the subsequent "pseudocode" article.
prerequisites are the files or targets required by the target to be generated.
command is the command that Mark needs to execute (arbitrary shell command).
This is a file dependency, that is to say, one or more target files of target depend on the files in prerequisites, and its production rules are defined in command. To put it bluntly, if there is more than one file in prerequisites than target If the file is new, the command defined by command will be executed. This is the rule of Makefile. It is also the core content of Makefile.