x86 CPU architecture

This article is the sixth lecture notes of "Interesting Talk about Linux Operating System" by Geek Time, link: 06 | x86 architecture: Only with an open architecture can we create an open business environment-Geek Time

 Intel's 8086 CPU architecture

Data unit : 8 16bit general-purpose registers, followed by 32bit extended bits

 

 control unit

The IP register is the instruction pointer register (Instruction Pointer Register), which points to the location of the next instruction in the code segment. 

What if you need to switch processes? Each process is divided into code segment and data segment. In order to point to the address space of different processes, there are four 16-bit segment registers, namely CS, DS, SS, and ES.

CS is the code segment register (Code Segment Register), through which you can find the location of the code in memory

DS is the register for the data segment, through which the location of the data in memory can be found.

SS is the stack register (Stack Register)

How many bits of address correspond to how much memory?

2^10 = K

2^20 = M

2^30 = G

2^16 = 2^6* 2^10 = 64 K

  • 32-bit address bus, can access 2^32=4GB of memory, a memory unit is 1B, 2^32 = 4*2^30 = 4GB
  • 20-bit address bus, can access 2^20 = 1MB of memory

The real mode when X86 starts, intelligently searches for 1M memory, and each segment is up to 64K. The 32-bit system in protected mode can address 4G memory.

Summarize

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Origin blog.csdn.net/Chunying27/article/details/127555711