Common CPU instruction set introduced

A, X86

A microprocessor executing computer language instruction set, referring to a standard abbreviation intel number series general purpose computer, a general-purpose computer also identifies a set of instructions, are CISC.

1.1 Introduction

US Intel X86 instruction set for its first piece of 16-bit CPU (i8086) specially developed for the United States, IBM in 1981 launched the world's first PC, the CPU? / FONT> i8088 (i8086 Starter Edition) to use X86 instruction is also to improve the floating-point data in computer processing capabilities increase the X87 family math coprocessor chip using the X87 instruction Further, after X87 and X86 instruction set will be a set of instructions referred to as X86 instruction set. Although with the development of CPU technology, Intel have developed a newer i80386, i80486 until today's Pentium Ⅲ (hereinafter abbreviated as PⅢ) series, but in order to ensure that the computer can continue to run all kinds of applications developed in the past to protect and inherit a wealth of software resources, the company produced all Intel CPU still continue to use the X86 instruction set, so it's still a CPU X86 series. Also in addition to Intel Corp., AMD and Cyrix and other manufacturers have also produced can use the X86 instruction set of CPU, because the CPU can run all these various software developed by Intel CPU, so the industry will these computer CPU column Intel's CPU is compatible products. Since the Intel X86 series and compatible CPU use the X86 instruction set, so today the formation of a large series and compatible with X86 CPU lineup. Of course, in the current desktop (portable) computers not all using X86 series CPU.

1.2 Features

x86 is a program in order to facilitate and improve the access efficiency of the memory chip design system, comprising two main characteristics: First, the use of microcode, the instruction set may be executed directly from the microcode memory, the new processor design, simply less increase transistor can execute the same instruction set, may also be prepared by a new instruction set program quickly; second is to have a large instruction set, the x86 has a format comprising a double operand, register to register, memory to register and various types of memory to the instruction register, for the realization of complex operations, the microprocessor and the various registers in addition to providing similar functions to the programmer to machine instructions, but also by a microprogram stored in a read only memory (ROM) is achieved highly functional, the primary microprocessor executes a series of command calculation after completion of analysis of each instruction to complete the desired function.

1.3, the advantages and disadvantages

Advantages: Advantages x86 instructions embodied in the system can shorten the new microcode instruction design time, upward compatibility allows CISC machine system, the new system can use an instruction set that contains the earlier system. In addition to the high-level language format of the micro-program instruction to match, so the compiler does not have to be rewritten.

Disadvantages:

Small-scale general-purpose registers, the x86 instruction set, only eight general purpose register, CPU did most of the time of accessing data in a memory, affect the execution speed of the entire system. And RISC systems tend to have a lot of general purpose registers, and the use of overlapping register windows register file and techniques, of the register resources are fully utilized
Effect of the decoder performance, the role of the decoder is to convert the variable length x86 instruction is a fixed length RISC-like instructions to the RISC core and. Decoded into micro and decoding hardware decoding for simple x86 instructions can be decoded as long as the hardware, faster, and experience the x86 instruction requires complex micro decoded and divide it into several pieces of simple instructions, and slower Very complicated.
Small addressing range, the user need constraints.
A single instruction of a different length, powerful computing capability, but relatively complex structure, difficult to CISC all integrated on one chip hardware.

1.4, assembly instructions

Data transfer instructions
Data transfer instructions
Logical operation instructions
Operation command string
Control transfer instruction
Processor control instructions
Protection directive

Two, X64

Also known as " the x86 -64", abbreviated as "x64", is a 64-bit microprocessor architecture and the corresponding instruction set one, is the Intel x86 architecture extension products, also belong to the CISC.

2.1 Introduction

"X86-64" 1999 by the AMD design, AMD first public 64 set to expand to IA-32 , called x86-64 (later renamed AMD64). Thereafter also Intel used, Intel now called "Intel 64", had used Clackamas Technology (CT), IA- 32e and EM64T before. More use of the outside world "x86-64" or "x64" to call this 64-bit architecture to remain neutral and not favor any vendor.

2.2 Features

Mostly compatible with the X86, both support 64-bit general-purpose registers , 64-bit integer and logical operations, as well as 64-bit virtual address . Designers also made many improvements to infrastructure, some major changes are as follows: new register, the address width longer, "No running" bit (NX-bit): AMD64 One feature is to have "prohibit running" (No -Execute, NX) bit, it can prevent the worm to buffer overflow ways to attack (also known as: buffer overflow attacks , buffer overflow).

2.3, the advantages and disadvantages

Because from X86, it is CSIC, so the X86 has a similar disadvantage compared with the X86, has the following advantages:

64-bit address space
Extended register group
Developers familiar command set
32 can be run on 64-bit operating system structure
32 may be used as the operating system

2.4, assembly instructions

Like the basic X86, X86 instruction at most X64 64-bit mode is effective. Directive is not used in 64-bit mode is not supported. Such as: BCD code arithmetic instructions.

Three, ARM

Once called Advanced RISC Machine (Advanced RISC Machine) earlier called the Acorn RISC Machine, it is a 32-bit reduced instruction set (RISC) processor architecture. As well as derivative products based on ARM designs, important products include Marvell 's XScale architecture and TI 's OMAP series. ARM family accounted for all 32-bit embedded processor 75%, becoming the most numerous among the world's 32-bit architecture. Is to increase the operating speed of processors designed chip architecture, its pipeline operation key technology to complete multiple instructions in a clock cycle. Belong to RISC.

3.1 Introduction

Mainly used for a router Conexant ARM processor is the computer company Acorn (Acorn Computers Ltd) in 1983 development plan. The team led by Roger Wilson and Steve Furber, set out to develop a new architecture, similar to the advanced MOS Technology 6502 processor. Acorn computers have a lot of construction on the 6502 architecture, it is possible to design a similar chip means that there is a great advantage for the company. In 1985, when the team developed a ARM1 Sample version, but's first "real" production-type ARM2 mass production the following year. ARM2 having the 32-bit data bus , 26-bit address space , and provides the addressing range of 16 32-bit 64 Mbyte of registers . These registers which as a (word size) of the program counter, the front and back of 6 bits to 2 bits of the processor status flag (Processor Status Flags). ARM2 is probably the world's most simple and practical 32-bit microprocessor , which houses only the 30,000 transistors (compared to six years after the Motorola 68000 which contains 70,000 particles). Mainly used in industrial / embedded and handheld devices.

3.2 Features

The main features of the ARM instruction set architecture: First, small size, low power consumption, low cost, high performance; second and most widely used data register in the register operations are completed, the instruction execution faster; Third, addressing modes flexible and simple, high efficiency; Fourth instruction length is fixed, the processing efficiency can be improved by multiple pipelined manner.

3.3, the advantages and disadvantages

Small size, low power, low cost, high performance;
Support the Thumb (16-bit) / ARM (32-bit) dual instruction set, can be well compatible with the 8/16-bit device; extensive use of registers, instruction execution faster; most data operations are completed in the register;
Flexible and simple addressing modes, high efficiency;
Fixed instruction length;
Pipeline processing mode
Load_store structure: In the RISC, are required to complete all of the calculations in the register. And the register and communication by a separate instruction memory to complete. In the CSIC, CPU memory can be operated directly.

3.4, assembly instructions

Arithmetic and logic instructions
Compare instructions
Jump instructions
Shift instruction
Program status word memory access instructions
Memory access instruction

Fourth, other

SSE instruction set

Streaming SIMD Extensions

Since the MMX instruction does not bring significantly enhance 3D gaming performance, the company in 1999 Intel Pentium III introduced the Streaming SIMD extended instruction sequence (SSE) CPU products. SSE compatible MMX instructions, which can be (single instruction multiple data techniques) a single clock cycle and a plurality of floating point processing in parallel to effectively increase the operation speed by the floating-point SIMD. In the MMX instruction set, the floating point processor 8 borrow registers, which results in a decrease in floating-point operations. And when the introduction of the SSE instruction set, Intel Corporation Pentium III CPU added in eight 128-bit registers dedicated SSE instructions. And SSE instruction register can run at full speed, ensuring the parallelism and floating point arithmetic. ^[1]

SSE2 instruction set

In the Pentium 4 CPU, Intel has developed a new set of instructions SSE2. This newly developed a total of 144 SSE2 instruction, including the conversion between floating point SIMD instruction, shaping SIMD instructions, SIMD floating-point and integer data, the data conversion in a few most MMX register. Wherein the improvement comprises the introduction of an important new data formats, such as: 128-bit SIMD integer operations and 64-bit double-precision floating-point math. In order to make better use of cache. Further, in the Pentium 4 also added a few instruction cache, allowing the programmer to control data has been cached. ^[1]

SSE3 instruction set

With respect to SSE2, SSE3 and 13 newly added new instructions, they are collectively referred to previously pni (prescott new instructions). In instruction 13, one for video decoding, two threads for synchronization, and the rest for complex mathematical operations, and a floating point to integer conversion SIMD floating-point operations. ^[1]

SSE4 instruction set

SSE4 instruction added 50 new increased performance, these instructions will help compile, media, character / text processing program and point to accelerate.

SSE4 instruction set as Intel's future "significantly enhance the video" part of the platform. Other video platform enhancements as well as Clear Video Technology (CVT) and the Unified Display Interface (UDI) support, where the former is a response to ATi AVIVO technology supports advanced decoding, post-processing and enhanced 3D features. ^[1]

3D Now! Extended instruction set

3D Now! Instruction set of AMD in 1998 to develop multimedia instruction set extensions, a total of 21 instructions. MMX instruction set for processing floating-point is not to strengthen the capacity weaknesses, focus on improving AMD's K6 series CPU processing power for 3D graphics. Due to limited instruction, 3D Now! Instruction set mainly for 3D games, and support for other business graphics application processing deficiencies.

EM64T instruction set of Intel Corporation EM64T (Extended Memory 64 Technology) i.e. Extended Memory 64 Technology. The technology provides for the application server and workstation platforms to expand memory addressability, have more memory address space, can bring greater application flexibility, in particular, will help enhance the audio and video editing, CAD design and other complex engineering software and games application software. Often said that the 64 refers to the AMD's 64-bit CPU, and Intel's EM64T is out of their own understanding of the meaning of 64, and 64 is another name for the corresponding AMD's.

RISC instruction set RISC instruction set is after the high-performance CPU development direction. It is the conventional CISC (complex instruction set) Rel. In contrast, RISC instruction format unification, type less, addressing less than the complex instruction set also. Using RISC instruction set architecture major ARM, MIPS.

3DNow! + Instruction Set

In the original set of instructions based on the instruction to 52, which contains part of the SSE instruction, the instruction set is mainly used for the new AMD on the CPU. ^[1]

AVX instruction set

Intel AVX instruction set SIMD computation performance enhancement while also follows the MMX / the SSE instruction set . But differences and MMX / SSE is to enhance the AVX instruction from the instruction's format, great changes took place. x86 (IA-32 / Intel 64 ) on the infrastructure for the prefix (Prefix), a new command is achieved, but also to more complex instructions is achieved, so as to enhance the performance of the x86 CPU.

AVX is not x86 CPU's instruction set extensions , can achieve higher efficiency, and CPU hardware compatibility is better, and also has enough room for expansion, and that all its new format command system-related. Smoother AVX architecture is the direction of development, in other words, get rid of the lack of traditional x86, based on the SSE instructions AVX also make the interface easier to use SSE instructions.

For the latest command coding system of AVX, Intel also gives a more detailed description, including the possibility of a significant expansion of the instruction set. For example, Sandy Bridge brings dual instruction combines multiplication of support. Thus can more easily achieve the expansion of 512bits and 1024bits. Launched in late 2008 to 2009 meniikoaCPU "Larrabee (LARAB)" processor, will use AVX instruction set. From the point of view status also began a new chapter in Intel AVX instruction set processor.

Common CPU instruction set introduced

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