原文：RISC-V Moving Toward Open Server Specification
Author: Agam Shah
Reprinted from: https://www.hpcwire.com/2023/07/24/risc-v-moving-toward-open-server-specification/
Chinese translation:
July 24, 2023
A specification that could standardize the development of RISC-V server chips and systems is currently being drafted by RISC-V International, an organization that handles the development of instruction set architectures.
This specification establishes a standard interface for all layers of server computing systems based on RISC-V technology. It can help companies deploy RISC-V servers in cloud computing environments, where software runs through virtualized CPUs rather than directly from hardware CPUs.
To be sure, it's still early days for server specs. The current iteration includes a system management controller, a system-on-chip module, a security layer, a boot system, and a virtualization layer.
"The RISC-V Server SoC (system on chip) specification defines a standardized set of capabilities on which portable system software, such as operating systems and hypervisors, can rely," RISC-V said in a document defining the specification. Present in RISC-V server SoCs." Link to the specification is available here.
RISC-V is a freely licensable instruction set architecture. Anyone can create a chip based on the architecture, but companies can also add their proprietary modules and sell those chips. RISC-V is supported by most of the top chip manufacturers, including Intel, AMD, Apple, Nvidia and Qualcomm.
The Open Compute Project also defines similar specifications for x86 and ARM servers, which are used by server manufacturers as a blueprint for building standardized data center products.
The RISC-V proposal also provides the basis for server systems to support technologies such as CXL, which is already supported by x86 and ARM server makers.
The upcoming CXL 3.0 specification provides a high-speed communication link between chips, memory and storage and has attracted interest from server hardware manufacturers because it could change the way data centers are built. The specification will reduce processing and bandwidth chokepoints by disaggregating compute and storage modules.
Server specifications are built on instruction set architecture technologies, such as the newer vector processing specification approved in recent years.
A number of RISC-V companies are building server chips, most notably Ventana and Esperanto.
The companies built their own proprietary modules on top of the basic instruction set architecture but said they would standardize to the latest specifications approved by RISC-V International.
Research institutions in Europe and the United States are experimenting with RISC-V microservers to develop and test software.
The proposal to create a server specification also reflects RISC-V's open-source ethos -- working together as a community to develop and improve the product.
"The reason we are a community ... is because we can share the burden," Mark Himelstein, chief technology officer of RISC-V International, said in a speech at last month's RISC-V Summit in Barcelona.
The goal is to prevent hardware and software fragmentation in the RISC-V community. RISC-V International hopes to avoid the fate of Android, which quickly fell into pieces as phone developers modified the operating system to suit their smartphone needs.
"We share the work of defining the ISA, we share the work of finding the hardware-software interface... We share the software burden. It means everything from boot code to applications," Himelstein said.
RISC-V is still not considered a viable server replacement for the x86 or ARM that dominate the data center market.
“When people say ‘Oh, RISC 5 is 10 years behind ARM,’ the answer is yes, but it doesn’t take 10 years to catch up. In a separate speech at the RISC-V Summit, Dave Ditzel, CEO of Esperanto Systems, said: “It will take a few years to catch up. "
Original English text:
July 24, 2023
A specification that could standardize the development of RISC-V server chips and systems is currently being drafted by RISC-V International, an organization that is handling the development of the instruction set architecture.
The specification establishes standard interfaces for various layers of server computing systems built on RISC-V technology. It could help companies deploy RISC-V servers in cloud computing environments, in which software runs off virtualized CPUs and not directly off hardware CPUs.
To be sure, the server spec is in its early stages. The current iteration includes system management controllers, system-on-chip modules, security layers, boot systems, and virtualization layers.
“The RISC-V server SoC (system on chip) specification defines a standardized set of capabilities that portable system software such as operating systems and hypervisors can rely on being present in a RISC-V server SoC,” RISC-V said in a document defining the specification. A link to the specification is availablehere.
RISC-V is an instruction-set architecture that is free to license. Anyone can create chips based on the architecture, but companies can also add their proprietary modules and sell those chips. RISC-V is backed by most of the top chipmakers, including Intel, AMD, Apple, Nvidia, and Qualcomm.
The Open Compute Project has also defined similar specs for x86 and ARM servers, which are used as blueprints by server makers to build standardized data-center products.
The RISC-V proposal also provides a base for server systems to support technologies like CXL, which is already backed by x86 and ARM server makers.
The upcoming CXL 3.0 spec provides a high-speed communication link between chips, memory, and storage, and is drawing interest from server hardware makers as it could change the way data centers are built. The spec will cut processing and bandwidth chokepoints by disaggregating compute and storage modules.
The server spec is built on top of technologies in the instruction set architecture such as the newer vector processing specification, which has been ratified in recent years.
Many RISC-V companies are building server chips, with the most notable being Ventana and Esperanto.
The companies have built their own proprietary modules on top of the base instruction set architecture but have said they would standardize to the latest specs ratified by RISC-V International.
Research organizations in the Europe and U.S. are experimenting with RISC-V microservers to develop and test software.
The proposal to create a server spec also reflects the open-source ethos of RISC-V — to jointly develop and improve a product as a community.
“The reason we’re a community at all…is we get to share the burden,” said Mark Himelstein, the chief technology officer at RISC-V International, during a recent presentation at a RISC-V Summit held last month in Barcelona.
The goal is to prevent hardware and software fragmentation in the RISC-V community. RISC-V International wants to avoid the fate of Android, which quickly fragmented as phone developers modified the OS to meet their smartphone needs.
“We share the work of defining the ISA, we share the work of finding the hardware-software interface… and we share the software burden. It means everything from boot code all the way up to applications,” Himelstein said.
RISC-V still is not considered a viable server alternative to x86 or ARM, which dominate the data center market.
“When people say ‘Oh, RISC five is 10 years behind ARM,’ the answer is yes, but it is not going to take 10 years to catch up. It will take a couple of years to catch up,” said Dave Ditzel, CEO of Esperanto Systems, during another presentation at the RISC-V Summit.
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About HS-2
The HS-2 RISC-V universal motherboard is a standard mATX motherboard designed for developers jointly developed by Pengfeng Technology and its partners. It is pre-installed with a software package customized and developed by Pengfeng Technology for RISC-V high-performance servers. Includes various standard benchmarks and supports V extensions
The GCC compiler, computing library, middleware and many typical server applications.
The HS-2 RISC-V general-purpose motherboard is equipped with a domestic RISC-V 64-core processor (SG2042). SG2042 is the highest-performance RISC-V processor currently in mass production. It is mainly designed for the needs of high-performance computing and is suitable for large computing power application scenarios such as scientific computing, engineering computing, AI computing, and fusion computing.
