ARM licensing fees are too expensive, tech giants want to switch to open source architecture RISC-V

Not long ago, Tesla joined the RISC-V Foundation and is considering using free RISC-V designs in new chips. So far, more than 100 technology companies including IBM, NXP, Western Digital, NVIDIA, Qualcomm, Samsung, Google, and Huawei have joined the RISC-V camp. The reason for this phenomenon is that on the one hand, the licensing fee of ARM is too expensive, and on the other hand, it is also because RISC-V provides a completely open instruction set, which is very promising to become the Linux of the CPU field.

It is precisely because they are optimistic about the future of RISC-V that many technology giants bet early when RISC-V is still a potential stock.

Birth of RISC-V

In 2010, a research team at the University of California, Berkeley was preparing to start a new project, and to design a CPU, it was necessary to choose an instruction set. However, the X86 instruction set was controlled by Intel, and the ARM instruction set was authorized. The fee is very expensive, and MIPS, SPARC, and PowerPC also have intellectual property issues.

In this case, the Berkeley research team decided to design a completely new instruction set from scratch. And this new instruction set needs to be able to satisfy processors of all sizes from microcontrollers to supercomputers. As often said in the industry, designing an instruction set is not a black technology, and using this instruction set to implement a CPU is a truly valuable work. The Berkeley research team completed the RISC-V instruction set in three months and released the first version of the instruction set publicly.

The first version of the instruction set contained less than 50 instructions and could be used to implement a processor with basic functions such as fixed-point arithmetic and privileged mode. If users need, they can also customize new instructions according to their own needs.

In this way, the instruction set is both streamlined and flexible. Subsequently, the Berkeley research team named this new instruction set RISC-V, RISC refers to the reduced instruction set, and V is the Roman letter, which stands for the fifth generation. Because Professor David Patterson of Berkeley has developed four generations of processor chips before this.

More importantly, the Berkeley research team completely opened up the RISC-V instruction set and used the BSD License open source protocol, which makes RISC-V unlike ARM, PowerPC and other instruction sets that require a paid license to use. And the BSD open source agreement gives users a lot of freedom, allowing users to modify and redistribute open source code, and also allow commercial software based on open source code to be released and sold. How to say, like Linux's GPL agreement, it restricts the behavior of commercial companies. The BSD open source agreement is different. Apple's iOS is based on the BSD kernel, but after using open source software, because the BSD open source agreement gives Apple a lot of freedom, Apple can still close iOS and make money in the commercial market.

RISC-V is also very valuable for academic institutions such as universities and research institutes. When working on a project, the team of researcher Bao Yungang from the Institute of Computing Technology of the Chinese Academy of Sciences initially chose SUN's Open Sparc T1. However, the community activity and software support of this processor are not good, and the independence is relatively poor. Then chose Micro Blaze, but this processor is not open source. Finally, I turned my attention to RISC-V and completed the scientific research project. Related technical achievements are used by Huawei on HiSilicon's ARM CPU.

It is precisely because RISC-V has chosen the BSD open source protocol that is very friendly to commercial companies, and because RISC-V has the advantages of both simplicity and flexibility, many commercial companies have paid attention to RISC-V.

RV12 RISC-V processor

RISC-V is expected to replicate the success of Linux

Currently, on the CPU, X86 and ARM are the two dominant players. However, these two overlords are very domineering, Intel simply does not allow any company other than AMD and VIA to use the X86 instruction set, and once AMD is acquired, the X86 instruction set authorization will be renegotiated. Even Transmeta wanted to play a sideball through translation, but it was dragged to death by Intel's patent lawsuit.

Similarly, ARM is better than Intel, but only better. They are also very stingy in instruction set authorization. Companies that have obtained ARM32 authorization can count on one hand. Although ARM64 authorization is more, the authorization fee is extremely expensive. French chip startup Greenwave said that if they use the ARM architecture, they must Spent $15 million in licensing fees. And after the authorization expires, whether to continue the authorization and the authorization fee must be renegotiated.

It is precisely because X86 and ARM are very strict in licensing that many large companies are very dissatisfied with Intel and ARM, and this just gives RISC-V such a rising star opportunity. Including Google, Huawei, IBM, Micron, NVIDIA, Qualcomm, Samsung, Western Digital and other commercial companies, as well as UC Berkeley, MIT, Princeton University, ETH Zurich, Indian Institute of Technology, Lorenz National Laboratory, Singapore Academic institutions such as Nanyang Technological University and the Institute of Computing Technology of the Chinese Academy of Sciences have joined RISC-V one after another. At the 7th RISC-V Workshop held in November 2017, a total of 138 companies, 35 universities and research institutions from around the world participated.

In addition to commercial companies and academic institutions, the Indian government has a soft spot for RISC-V. In 2011, India began to implement the processor strategic plan, funding 2-3 projects to develop processors across the country. The SHAKTI processor project was started by Prof. GS Madhusudan and V. Kamakoti from the Indian Institute of Technology Madras with the support of this program. The SHAKTI project chose RISC-V and received more than $90 million in funding from the Indian government.

In 2016, the Advanced Computing Development Center of India received a $45 million grant from the Indian Ministry of Electronics and Information Technology to develop a 2GHz quad-core processor based on the RISC-V instruction set.

In the past few years, processor-related projects funded by the Indian government have begun to move closer to RISC-V, which has become India's de facto national instruction set.

At present, the Berkeley research team has completed the sequential execution of the 64-bit processor core (code-named Rocket) based on the RISC-V instruction set, and has conducted 12 tapeouts based on the 45nm and 28nm processes. The Rocket chip's main frequency is greater than 1GHz. Compared with the ARM Cortex-A5, the measured performance is 10% higher, the area efficiency is 49% higher, and the dynamic power consumption per frequency is only 43% of the Cortex-A5. In the embedded field, Rocket can already compete with ARM in the market.

It is for this reason that Western Digital announced that it will use 1 billion RISC-V cores per year; Nvidia also announced that it will use RISC-V for the controller inside the GPU. DARPA in the United States has also funded some companies to design aerospace chips for spacecraft based on RISC-V; many commercial companies plan to develop IoT-oriented smart chips, security-oriented chips, and motherboard management controllers on servers based on RISC-V. In terms of software ecology, it is also gradually improving. For example, the debugging tool chain, interrupt controller, JVM, LLVM, Python and other software tools commonly used by developers are being improved.

It is by relying on open source and free, commercial companies and academic institutions all over the world can develop processors compatible with the RISC-V instruction set without paying a penny. This makes RISC-V expected to be widely used by developers around the world and replicate the wonders of Linux. What's more, the BSD open source protocol of RISC-V is more friendly to commercial companies than the GPL protocol, so that commercial companies have a strong incentive to promote this matter.

Epilogue

It is true that, relying on open source and free, RISC-V is very popular with universities and research institutes, and is expected to show its strength in the field of teaching, which in turn will cultivate a continuous reserve army for RISC-V. For commercial companies, since the licensing fee of ARM is too expensive, there is also a strong incentive to do RISC-V, leaving a backup for themselves to avoid being tied to ARM.

However, RISC-V also has a hidden concern, that is, the lack of a strong leader, which leads to the problem of fragmentation. The MIPS of that year was actually very academic. Commercial companies in the MIPS camp were free to add instructions. For example, Godson added more than 1,000 new instructions based on MIPS, and then formed its own instruction set, LoongISA. This makes software development, even if it also belongs to MIPS, it must be divided into Loongson version and MIPS version...

Since RISC-V also allows users to add new instructions by themselves, this may break RISC-V. Perhaps in the future, RISC-V processors developed by Huawei, Qualcomm, and Google belong to RISC-V, but they cannot run the same A set of software.

After all, complete openness and strong leadership are a pair of contradictions. If this problem cannot be solved, I am afraid that it will be difficult for RISC-V to grow to the level where it can compete with X86 and ARM.

From: Lei Feng Network