Freehand implementation of RISC-V

1. Take the ADD instruction as an example

 2. Three-stage pipeline operation

         First of all, the ADD instruction does not design memory access operations.

3. Module design

 4. Precautions

Immediate operation, pay attention to sign bit extension.

Since the x0 register is always 0, no operation can be realized;

 

MOV instruction can be realized by adding zero;

Type I instructions:

 R-type command:

5. Pipeline flushing

Source code + course explanation: teach you how to design RISC-V processor Phase 0 - ready to go_哔哩哔哩_bilibili