Regarding the birth experience of RISC-V at the University of Berkeley, I will not repeat it here in this section.
Because many free or open architectures have appeared in the CPU field over the years, many universities have also introduced multiple instruction set architectures in scientific research projects. Therefore, when I first heard about RISC-V, I thought it was a toy or a purely academic research project.
Until the author personally read through the RISC-V architecture document, I couldn't help being impressed by its advanced design concept. At the same time, the various advantages of the RISC-V architecture have also been favored by many professionals and many commercial companies have joined one after another. And the official launch of the RISC-V Foundation in 2016 has caused a lot of influence in the industry. All of these make RISC-V the most revolutionary open processor architecture so far.
1 Simple is beautiful --RISC-V architecture design philosophy
The RISC-V architecture is an instruction set architecture. Before introducing the details, let us first understand the design philosophy. The so-called "philosophy" of design is one of its strategies. For example, the design philosophy of Japanese cars as we know it is economical and fuel-efficient, and the design philosophy of American cars is domineering and leaking. What is the design philosophy of the RISC-V architecture? It is "Away to Jane".
One of the design principles that the author advocates most is: simplicity is beauty, and simplicity means reliability. Numerous actual cases have confirmed the truth that "simple means reliable", on the contrary, the more complex the machine, the more error-prone it is.
The so-called road is simple, in the actual work of IC design, the author has seen the simplest design to achieve safety and reliability, and has also seen the most complicated design unable to converge stably for a long time. The simplest design is often the most reliable, and has been tested again and again in most project practices.
The nature of the work of IC design is very special. The final output is a chip. The design and manufacturing cycle of a chip is very long. It cannot be upgraded and patched as easily as software code. Every chip revision is required to be delivered. Cycle of several months. Not only that, the one-time manufacturing cost of the chip is high, ranging from hundreds of thousands of dollars to tens of millions of dollars. These characteristics all determine that the trial and error cost of IC design is extremely high, so it is very important to be able to effectively reduce the occurrence of errors.
The scale of modern chip design is getting bigger and bigger, and the complexity is getting higher and higher. It does not mean that designers are required to avoid using complicated technology blindly, but that good steel should be used on the blade and the most complicated design should be used in the most For critical scenarios, in most cases where there is a choice, try to choose a concise implementation scheme.
When the author read the RISC-V architecture document for the first time, I couldn’t help but admire and be surprised, because the RISC-V architecture constantly and clearly emphasized in its documents that its design philosophy is "road to simplicity", trying to adopt the architecture The definition makes the hardware implementation simple enough. Its simplicity is the philosophy of beauty, which can be easily seen from several aspects, which will be discussed in subsequent sections.
1.1 Disease-free and light-weight-the length of the architecture
In the processor field, the current mainstream architectures are x86 and ARM architectures. The author once participated in the design of ARM architecture application processors. Therefore, it is necessary to read the ARM architecture documents. Readers who are familiar with it should understand its length. After decades of development, the architecture documents of modern x86 and ARM architectures are as long as hundreds of thousands of pages. It can be half the height of a table when printed, but it is really "a book waiting for the body".
One of the main reasons why the modern x86 and ARM architecture documents are thousands of pages long and there are many versions is that the development process of their architecture is accompanied by the continuous development and maturity of modern processor architecture technology.
And as a commercial architecture, in order to maintain the backward compatibility of the architecture, it has to retain many outdated definitions, or it is very awkward to define new architecture parts in order to be able to integrate the existing technical parts. Over time it becomes extremely lengthy.
So whether the modern mature architecture can choose to start again and redefine a concise architecture, it can be said that it is almost impossible. One of the important reasons is that it is not forward compatible, and thus cannot be accepted by users. Imagine that if we buy a new computer or mobile phone with a new processor and go home, all the previous software cannot run and become bricks. It is definitely unacceptable.
The RISC-V architecture, which has only been launched now, has the advantage of latecomer. As the computer architecture has become a relatively mature technology after years of development, the problems exposed in the process of continuous maturity over the years have been thoroughly studied, so The new RISC-V architecture can be circumvented, and it does not carry the historical baggage of backward compatibility. It can be said that it is disease-free and light.
The current "RISC-V architecture documents" are divided into "instruction set documents" (riscv-spec-v2.2.pdf) and "privileged architecture documents" (riscv-privileged-v1.10.pdf). The "instruction set document" is 145 pages long, while the "privileged architecture document" is only 91 pages long. Engineers who are familiar with the architecture can read it through within one to two days. Although the "RISC-V architecture document" is still being enriched, compared to the "x86 architecture document" and the "ARM architecture document", RISC- V's length can be said to be extremely short and concise.
Interested readers can download its documents for free on the RISC-V Foundation website (https://riscv.org/specifications/) without registration, as shown in Figure 1.
Figure 1 Architecture documents on the RISC-V Foundation website
1.2 Flexibility and extension-modular instruction set
The biggest difference between the RISC-V architecture and other mature commercial architectures is that it is a modular architecture. Therefore, the RISC-V architecture is not only short and succinct, but its different parts can also be organized together in a modular manner, so as to try to satisfy a variety of different applications through a unified architecture.
This kind of modularity is not available in the x86 and ARM architectures. Take the architecture of ARM as an example. The architecture of ARM is divided into three series, A, R and M, which are respectively aimed at the three fields of Application (application operating system), Real-Time (real-time) and Embedded (embedded). Not compatible.
However, the modular RISC-V architecture enables users to flexibly choose different module combinations to meet different application scenarios, which can be said to be suitable for all ages. For example, for small-area and low-power embedded scenarios, users can choose the instruction set of the RV32IC combination and only use Machine Mode; while for high-performance application operating system scenarios, they can choose the instruction set such as RV32IMFDC and use Machine Mode ( Machine mode) and User Mode (user mode) two modes. And their common parts can be compatible with each other.
1.3 What is concentrated is the essence-the number of instructions
The short and compact architecture and modular philosophy make the number of instructions in the RISC-V architecture very concise. The number of basic RISC-V instructions is only more than 40, and there are dozens of instructions in total with other modular extension instructions.
2 Introduction to RISC-V instruction set architecture
This chapter will briefly introduce the many aspects of the RISC-V instruction set architecture.
2.1 Modular instruction subset
The RISC-V instruction set is organized in a modular manner, and each module is represented by an English letter. The most basic and only mandatory instruction set part of RISC-V is the basic integer instruction subset represented by the letter I. Using this integer instruction subset, a complete software compiler can be implemented. Other instruction subsets are optional modules, and representative modules include M/A/F/D/C, as shown in Table 1.
Table 1 Modular instruction set of RISC-V
In order to increase code density, the RISC-V architecture also provides an optional "compressed" instruction subset, represented by the English letter C. The instruction encoding length of the compressed instruction is 16 bits, while the length of the ordinary uncompressed instruction is 32 bits. A specific combination of the above modules "IMAFD", also known as "universal" combination, is represented by the English letter G. Therefore RV32G means RV32IMAFD, and RV64G means RV64IMAFD in the same way.
In order to further reduce the area, the RISC-V architecture also provides an "embedded" architecture, represented by the English letter E. This architecture is mainly used in deep embedded scenarios that pursue extremely low area and power consumption. This architecture only needs to support 16 general-purpose integer registers, while the non-embedded general architecture needs to support 32 general-purpose integer registers.
Through the above modular instruction set, different combinations can be selected to meet different applications. For example, the RV32EC architecture can be chosen for embedded scenes that pursue small area and low power consumption; while the large 64-bit architecture can choose RV64G.
In addition to the above-mentioned modules, there are several modules including L, B, P, V, and T. Most of these extensions are still being refined and defined, and have not yet been finalized, so this article will not discuss them in detail here.
2.2 Configurable general register bank
The RISC-V architecture supports a 32-bit or 64-bit architecture. The 32-bit architecture is represented by RV32, and the width of each general-purpose register is 32 bits; the 64-bit architecture is represented by RV64, and the width of each general-purpose register is 64 bits.
The integer general register set of the RISC-V architecture contains 32 (I architecture) or 16 (E architecture) general integer registers, of which integer register 0 is reserved as a constant 0, and the other 31 (I architecture) or 15 (E architecture) is an ordinary general-purpose integer register.
If a floating-point module (F or D) is used, another independent floating-point register group is required, which contains 32 general-purpose floating-point registers. If only the floating-point instruction subset of the F module is used, the width of each general-purpose floating-point register is 32 bits; if the floating-point instruction subset of the D module is used, the width of each general-purpose floating-point register is 64 bits.
2.3 Regular instruction coding
It is often one of the expectations of processor pipeline design to be able to read the general register set as soon as possible in the pipeline, which can improve processor performance and optimize timing. This seemingly simple truth is difficult to implement in many existing commercial RISC architectures, because after years of repeated modification and continuous addition of new instructions, the register index position in the instruction encoding has become very messy, causing a burden on the decoder. .
Benefiting from the advantages of latecomers and summing up the lessons of processor development over the years, RISC-V's instruction set coding is very regular, and the indexes of general registers required for instructions (Index) are placed in a fixed position, as shown in Figure 2. Shown. Therefore, the Instruction Decoder can easily decode the register index and then read the general register file (Register File, Regfile).
Figure 2 RV32I regular instruction encoding format
2.4 Concise memory access instructions
Like all RISC processor architectures, the RISC-V architecture uses dedicated memory read (Load) instructions and memory write (Store) instructions to access the memory, and other ordinary instructions cannot access the memory. This architecture is based on the RISC architecture. A commonly used basic strategy, this strategy makes the hardware design of the processor core simple.
The basic unit of memory access is byte (Byte). RISC-V memory read and memory write instructions support one byte (8 bits), half word (16 bits), single word (32 bits) as the unit of memory read and write operations. If it is a 64-bit architecture, it can also support a double word (64-bit) is a unit of memory read and write operations.
The memory access instructions of the RISC-V architecture also have the following notable features:
- In order to improve the performance of memory read and write, the RISC-V architecture recommends the use of address-aligned memory read and write operations, but the RISC-V architecture also supports memory operations with non-aligned addresses. The processor can choose to support hardware or software. Come to support.
- Since the current mainstream application is the Little-Endian format, the RISC-V architecture only supports the Little-Endian format. Regarding the definition and difference between little-endian format and big-endian format, this article will not introduce too much here, if beginners who don't know this well can check and learn by themselves.
- Many RISC processors support the address auto-increment or auto-decrement mode. Although this auto-increment or auto-decrement mode can improve the performance of the processor to access the continuous memory address range, it also increases the difficulty of designing the processor. The memory read and memory write instructions of the RISC-V architecture do not support the address auto-increment and auto-decrement mode.
- The RISC-V architecture uses a relaxed memory model (Relaxed Memory Model). The loose memory model does not require the execution order of memory read and write instructions that access different addresses, unless it is shielded by a clear memory barrier (Fence) instruction.
These choices clearly reflect the RISC-V architecture's attempt to simplify the basic instruction set, thereby simplifying the philosophy of hardware design. The definition of RISC-V architecture is very reasonable, and it can achieve the effect of flexion and extension. For example, for a simple CPU with low power consumption, a very simple hardware circuit can be used to complete the design; for a superscalar processor that pursues high performance, the performance can be improved through the dynamic hardware scheduling capability of a complex design.
2.5 Efficient branch and jump instructions
The RISC-V architecture has two unconditional jump instructions (Unconditional Jump), jal and jalr instructions. The jump link (Jump and Link) instruction jal can be used to call a subroutine, and the return address of the subroutine is stored in the link register (Link Register: a general integer register). The jump link register (Jump and Link-Register) instruction jalr instruction can be used for the subroutine return instruction. By using the link register saved by the jal instruction (jump into the subroutine) as the base address register of the jalr instruction, you can The program returns.
The RISC-V architecture has 6 conditional branch instructions. This conditional branch instruction directly uses 2 integer operands like ordinary arithmetic instructions, and then compares them. If the comparison conditions are met When, then jump. Therefore, this type of instruction puts the two operations of comparison and jump into one instruction.
As a comparison, many other RISC architecture processors need to use two independent instructions. The first instruction uses a comparison instruction first, and the result of the comparison is stored in the status register; the second instruction uses a jump instruction, and jumps when the comparison result of the previous instruction stored in the status register is judged to be true. In comparison, the conditional jump instruction of RISC-V not only reduces the number of instructions, but also has a simpler hardware design.
For low-end CPUs that are not equipped with a hardware branch predictor, in order to ensure its performance, the RISC-V architecture clearly requires it to adopt the default static branch prediction mechanism, that is: if it is a conditional jump instruction that jumps backward, the prediction is "Jump"; if it is a conditional jump instruction that jumps forward, the prediction is "no jump", and the RISC-V architecture requires the compiler to compile and generate assembly code according to this default static branch prediction mechanism, so that Low-end CPUs can also get good performance.
In order to make the hardware design as simple as possible, the RISC-V architecture specifically defines that the offset of all conditional jump instructions (relative to the address of the current instruction) is a signed number, and the sign bit is encoded in a fixed s position. Therefore, this static prediction mechanism is very easy to implement in hardware. The hardware decoder can easily find this fixed position and determine whether it is 0 or 1 to determine whether it is a positive or negative number. If it is a negative number, it means a jump The target address is the current address minus the offset, which is a backward jump, and it is predicted as a "jump". Of course, for high-end CPUs equipped with hardware branch predictors, advanced dynamic branch prediction mechanisms can be used to ensure performance.
2.6 Concise subroutine call
In order to understand this section, it is necessary to introduce the process of calling sub-functions in the general RISC architecture. The process is as follows:
- After entering the sub-function, you need to use a memory write (Store) instruction to save the current context (values of general-purpose registers, etc.) to the stack area of the system memory. This process is usually called "save the scene".
- When exiting the subroutine, you need to use the memory read (Load) instruction to read the previously saved context (values of general-purpose registers, etc.) from the stack area of the system memory. This process is usually called "recovering the scene".
The process of "save site" and "restore site" is usually completed by the instructions generated by the compiler. Developers who use high-level languages (such as C or C++) do not need to care too much about this. A sub-function call can be written directly in the program of the high-level language, but the process of "saving the scene" and "recovering the scene" at the bottom layer is actually happening (you can see from the compiled assembly language Those assembly instructions for "save the scene" and "restore the scene"), and also consume a certain amount of CPU execution time.
In order to speed up the process of "saving the scene" and "recovering the scene", some RISC architectures invented instructions to write multiple registers to the memory at once (Store Multiple), or read multiple registers from the memory at once (Load Multiple). , The advantage of this type of instruction is that one instruction can accomplish many things, thereby reducing the amount of assembly instruction code and saving code space. However, the disadvantage of such "Load Multiple" and "Store Multiple" is that it will complicate the hardware design of the CPU, increase the hardware overhead, and may damage the timing so that the main frequency of the CPU cannot be increased. The author once designed this type of processor It suffers from time to time.
The RISC-V architecture abandons the use of such "Load Multiple" and "Store Multiple" instructions. And explain that if there are occasions where you are more concerned about the number of instructions for “save the scene” and “restore the scene”, you can use a public library (specially used for saving and restoring the scene) to do so, so that you can save on In the process of each sub-function call, a different number of "save site" and "restore site" instructions are placed.
This choice once again confirms RISC-V’s philosophy of pursuing hardware simplicity, because abandoning the "Load Multiple" and "Store Multiple" instructions can greatly simplify the hardware design of the CPU. For low-power and small-area CPUs, you can choose a very simple circuit for implementation. , And the high-performance superscalar processor has strong hardware dynamic scheduling capabilities, and can have a powerful branch prediction circuit to ensure that the CPU can quickly jump execution, so you can choose to use a common library (specially used to save and restore the scene) Ways to reduce the amount of code, but at the same time achieve high performance.
2.7 Unconditional code execution
Many early RISC architectures invented instructions with condition codes. For example, the first few bits of the instruction code indicate the condition code (Conditional Code). Only when the condition corresponding to the condition code is true, the instruction is actually executed.
This form of encoding condition codes into instructions allows the compiler to compile short loops into instructions with condition codes instead of compiling into branch jump instructions. This reduces the occurrence of branch jumps, on the one hand, reduces the number of instructions; on the other hand, it also avoids the performance loss caused by branch jumps. However, the drawbacks of this "condition code" instruction will also complicate the hardware design of the CPU, increase the cost of the hardware, and may damage the timing so that the CPU's main frequency cannot be increased. The author once designed this type of processor. Suffer from it.
The RISC-V architecture abandons the use of this "condition code" instruction, and uses ordinary conditional branch jump instructions for any conditional judgment. This choice once again confirms RISC-V’s philosophy of pursuing simple hardware, because abandoning the "condition code" instruction can greatly simplify the hardware design of the CPU. For low-power and small-area CPUs, you can choose a very simple circuit for implementation. The high-performance superscalar processor has strong hardware dynamic scheduling capabilities and can have a powerful branch prediction circuit to ensure that the CPU can quickly jump execution to achieve high performance.
2.8 No branch delay slot
Many early RISC architectures used "Delay Slot". The most representative one is the MIPS architecture. In many classic computer architecture textbooks, MIPS has been used to introduce the branch delay slot. The branch delay slot means that one or several instructions immediately following each branch instruction are not affected by the branch jump. No matter whether the branch is jumped or not, the following instructions will be executed.
Many early RISC architectures adopted branch delay slots. The main reason for the birth of branch delay slots was that the processor pipeline at that time was relatively simple and did not use advanced hardware dynamic branch predictors, so the use of branch delay slots can achieve considerable performance effects. However, this branch delay slot makes the hardware design of the CPU extremely awkward, and CPU designers often suffer from this.
The RISC-V architecture abandons the branch delay slot, and once again confirms the philosophy of RISC-V to simplify the hardware, because the branch prediction algorithm accuracy of modern high-performance processors is already very high, and powerful branch prediction circuits can ensure that the CPU can be accurate. The predictive jump execution achieves high performance. For low-power and small-area CPUs, since there is no need to support branch delay slots, the hardware is greatly simplified, which can further reduce power consumption and improve timing.
2.9 No zero-overhead hardware loop
Many RISC architectures also support Zero Overhead Hardware Loop (Zero Overhead Hardware Loop) instructions. The idea is to directly participate in the hardware, by setting certain loop count registers (Loop Count), and then the program can be automatically looped, each cycle Then Loop Count is automatically decremented by 1, so continue to loop until the value of Loop Count becomes 0, then exit the loop.
The reason why this hardware-assisted zero-overhead loop is proposed is because the for loop in the software code (for i=0; i
However, there are gains and losses, such zero-overhead hardware loop instructions greatly increase the complexity of hardware design. Therefore, zero-overhead loop instructions are completely opposite to the philosophy of RISC-V architecture to simplify hardware. Naturally, such zero-overhead hardware loop instructions are not used in the RISC-V architecture.
2.10 Concise arithmetic instructions
In Section 2.1 of this chapter, it was mentioned that the RISC-V architecture uses a modular approach to organize different instruction subsets. The most basic integer instruction subset (indicated by the letter I) supports operations including addition, subtraction, shift, and bitwise. Logical operations and comparison operations. These basic arithmetic operations can complete more complex operations (such as multiplication and division and floating-point operations) through combination or function libraries, so that most software operations can be completed.
The operations supported by the integer multiplication and division instruction subset (indicated by the letter M) include signed or unsigned multiplication and division operations. The multiplication operation can support the multiplication of two 32-bit integers to obtain a 64-bit result; the division operation can support the division of two 32-bit integers to obtain a 32-bit quotient and a 32-bit remainder.
The single-precision floating-point instruction subset (indicated by the letter F) and double-precision floating-point instruction subset (indicated by the letter D) support operations including floating-point addition and subtraction, multiplication and division, multiplication and accumulation, square root extraction, and comparison operations. Format conversion operations between integer and floating point, single precision and double precision floating point.
Many RISC architecture processors will produce software exceptions when errors occur in arithmetic instructions, such as overflow, underflow, subnormal, and division by zero. A special feature of the RISC-V architecture is that no exceptions are generated for any arithmetic instruction errors (including integer and floating-point instructions), but a special default value is generated, and at the same time, the status bits of certain status registers are set. The RISC-V architecture recommends that the software find these errors through other methods. Once again clearly reflects the RISC-V architecture strives to simplify the basic instruction set, thereby simplifying the philosophy of hardware design.
2.11 Elegant compression instruction subset
The basic RISC-V basic integer instruction subset (indicated by the letter I) specifies the instruction lengths are all equal length 32 bits. This equal length instruction definition makes it very easy to design a basic RISC-V CPU that only supports an integer instruction subset. However, the same length 32-bit encoding instructions will also cause a relatively large code size problem.
In order to meet certain scenarios with high code size requirements (such as the embedded field), RISC-V defines an optional compressed (Compressed) instruction subset, which is represented by the letter C or RVC. RISC-V has the advantage of being late. Compressed instructions are planned from the beginning, and enough coding space is reserved. 16-bit long instructions and ordinary 32-bit long instructions can be seamlessly and freely intertwined, and the processor is not defined. Extra status.
Another special feature of RISC-V compression instructions is that the compression strategy of 16-bit instructions is to compress and rearrange the information in a part of the most commonly used 32-bit instructions (for example, suppose an instruction uses two identical operations Number index, you can save the coding space of one of the indexes), so each 16-bit instruction can find its corresponding original 32-bit instruction one by one. Therefore, program compilation into compressed instructions can be completed only in the assembler stage, which greatly simplifies the burden of the compiler tool chain.
The researchers of the RISC-V architecture conducted a detailed code volume analysis. As shown in Figure 3, it can be seen from the analysis results that the code volume of RV32C is reduced by 40% compared to the code volume of RV32, and compared with ARM, MIPS has a good performance compared with x86 and other architectures.
Figure 3 Comparison of code density of each instruction set architecture (the smaller the data, the better)
2.12 Privileged Mode
The RISC-V architecture defines three working modes, also known as Privileged Mode:
- Machine Mode: Machine mode, referred to as M Mode.
- Supervisor Mode: Supervisor Mode, referred to as S Mode.
- User Mode: User mode, referred to as U Mode.
The RISC-V architecture defines M Mode as a required mode, and the other two as optional modes. Different systems can be realized through different mode combinations.
The RISC-V architecture also supports several different memory address management mechanisms, including the management mechanism for physical addresses and virtual addresses, so that the RISC-V architecture can support from simple embedded systems (directly manipulate physical addresses) to complex operating systems (Direct manipulation of virtual addresses) various systems.
2.13 CSR Register
The RISC-V architecture defines some control and status registers (Control and Status Register, CSR), which are used to configure or record some operating status. The CSR register is an internal register of the processor core. The use of its own address coding space has nothing to do with the address range of the memory addressing.
CSR register access uses dedicated CSR instructions, including CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI and CSRRCI instructions.
2.14 Interrupts and exceptions
Interrupt and exception mechanisms are often the most complex and critical parts of the processor's instruction set architecture. The RISC-V architecture defines a relatively simple and basic interrupt and exception mechanism, but it also allows users to customize and extend it.
2.15 Vector instruction subset
Although the RISC-V architecture does not have a finalized vector instruction subset, it can be seen from the current draft that the design concept of the RISC-V vector instruction subset is very advanced, due to the late-comer advantage and the use of vector architecture The conclusion of many years of mature development is that the RISC-V architecture will use variable-length vectors instead of vector fixed-length SIMD instruction sets (such as ARM's NEON and Intel's MMX), so that it can flexibly support different implementations. CPUs that pursue low power consumption and small area can choose to use shorter hardware vectors for implementation, while high-performance CPUs can choose longer hardware vectors for implementation, and the same software codes can be compatible with each other.
2.16 Custom instruction extension
In addition to the extensibility and selection of the modular instruction subset described above, the RISC-V architecture also has a very important feature, which is to support third-party extensions. Users can extend their own instruction subsets. RISC-V reserves a large amount of instruction coding space for user-defined extensions. At the same time, four Custom instructions are defined for users to use directly. Each Custom instruction has several The bit sub-coding space is reserved, so users can directly use four Custom commands to expand dozens of custom commands.
2.17 Summary and comparison
After decades of development of processor design technology, with the development of large-scale integrated circuit design technology to this day, it has the following characteristics:
- Because the hardware scheduling capability of high-performance processors is already very strong and the main frequency is very high, the hardware design hopes that the instruction set is as regular and simple as possible, so that the processor can design a higher frequency and a lower area. .
- Very low-power processors based on IoT applications are more demanding for low power consumption and low area.
- The memory resources are also more abundant than earlier RISC processors.
All of the above factors have made many early RISC architecture design concepts (born based on the technical background of the time) not only unable to help modern processor design, but also becoming a burden. Certain features defined by the early RISC architecture, on the one hand, made the hardware design of high-performance processors constrained; on the other hand, they burdened the hardware design of extremely low-power processors with unnecessary complexity.
Benefiting from the advantage of latecomer, the new RISC-V architecture can circumvent all these known burdens, and at the same time, use its advanced design philosophy to design a set of "modern" instruction sets. This section summarizes its characteristics again as shown in Table 2.
Table 2 Summary of RISC-V instruction set architecture characteristics
