[STM32] ADC details

00. Table of Contents

01. Introduction to ADC

The 12-bit ADC is a successive approach analog-to-digital converter. It has up to 19 multiplexed channels and can measure signals from 16 external sources, two internal sources and V BAT channels. The A/D conversion of these channels can be performed in single, continuous, sweep or discontinuous sampling modes. The ADC result is stored in a left-justified or right-justified 16-bit data register. The ADC has an analog watchdog feature, allowing the application to detect whether the input voltage exceeds the user-defined upper or lower threshold.

02. ADC main features

● Configurable 12-bit, 10-bit, 8-bit or 6-bit resolution
● Interrupts are generated at the end of conversion, end of injection conversion, and analog watchdog or overflow event
● Single and continuous conversion mode
● Used to automatically change channel 0 Scan mode converted to channel "n"
● Data alignment to maintain built-in data consistency
● The sampling time of each channel can be set independently
● External trigger option, polarity can be configured for regular conversion and injection conversion
● Discontinuous sampling mode
● Double/ Triple mode (provided by devices with 2 or more ADCs)
● Configurable DMA data storage in dual/triple ADC mode
● Configurable delay between conversions in dual/triple alternate mode
● ADC conversion type (see data sheet)
● ADC power requirements: 2.4 V to 3.6 V at full speed, 1.8 V at slow speed
● ADC input range: V REF—  V IN  V REF+
● DMA requests can be generated during regular channel conversion

Note: V REF—If available (depending on package), it must be connected to V SSA.

03. ADC function description

block diagram

04. ADC switch control

The ADC can be powered by setting the ADON bit in the ADC_CR2 register to 1. When the ADON bit is set to 1 for the first time, the ADC will wake up from power-down mode.

When SWSTART or JSWSTART is set to 1, AD conversion is started.

The conversion can be stopped by clearing the ADON bit and put the ADC into power-down mode. In this mode, the ADC consumes almost no power (only a few μA)

05. ADC clock

The ADC has two clock schemes:
● The clock used in the analog circuit: ADCCLK, which is shared
by all ADCs comes from the APB2 clock divided by the programmable prescaler, which allows the ADC to be at f PCLK2 / 2, Work at /4, /6 or /8. Refer to the data sheet for the maximum value of ADCCLK.
● Clock used for digital interface (used for register read/write access)
This clock is equivalent to the APB2 clock. The digital interface clock can be enabled/disabled for each ADC through the RCC APB2 peripheral clock enable register (RCC_APB2ENR).

06. Channel selection

There are 16 multiplexed channels. The conversion can be divided into two groups: rule conversion and injection conversion. Each group contains a conversion sequence, which can be completed on any channel in any order. For example, the sequence can be converted in the following order: ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0, ADC_IN2, ADC_IN2, ADC_IN15.

● A rule conversion group consists of up to 16 conversions. The regular channels and order of the conversion sequence must be selected in the ADC_SQRx register. The total number of conversions in the regular conversion group must be written into the L[3:0] bits in the ADC_SQR1 register.
● An injection conversion group consists of up to 4 conversions. The injection channel and sequence of the conversion sequence must be selected in the ADC_JSQR register. The total number of conversions injected into the conversion group must be written into the L[1:0] bits in the ADC_JSQR register

If the ADC_SQRx or ADC_JSQR register is modified during the conversion, the current conversion will be reset and a new start pulse will be sent to the ADC to convert the newly selected group.

Temperature sensor, V REFINT and V BAT internal channels

● For STM32F40x and STM32F41x devices, the temperature sensor is internally connected to the channel ADC1_IN16. The internal reference voltage VREFINT is connected to ADC1_IN17.
● For STM23F42x and STM32F43x devices, the temperature sensor is internally connected to the channel ADC1_IN18 shared with VBAT. Only one conversion (temperature sensor or VBAT) can be selected at a time. When the temperature sensor and VBAT conversion are set at the same time, only VBAT conversion will be performed.

The internal reference voltage VREFINT is connected to ADC1_IN17.
The V BAT channel is connected to channel ADC1_IN18. The channel can also be converted into an injection channel or a regular channel.
Note: The temperature sensor, V REFINT and V BAT channels are only available on the main ADC1 peripheral.

07. Conversion mode

Single conversion mode

In single conversion mode, the ADC performs one conversion. When the CONT bit is 0, this mode can be started in the following ways:
● Set the SWSTART bit in the ADC_CR2 register to 1 (only for regular channels)
● Set the JSWSTART bit to 1 (for injection channels)
● External trigger (for regular channels or Injection channel)

After the conversion of the selected channel:
● If the conversion rule channel:
- converts the data stored in the register 16 ADC_DR
- EOC (end of conversion) flag. 1
- EOCIE position interrupt is generated. 1
● If converted injection channel:
- The conversion data is stored in the 16-bit ADC_JDR1 register
-the JEOC (injected conversion end) flag is set to 1
-an interrupt is generated when the JEOCIE bit is set to 1,
and then the ADC stops.

Continuous conversion mode

In continuous conversion mode, the ADC starts a new conversion immediately after finishing a conversion. When the CONT bit is 1, this mode can be started by an external trigger or by setting the SWSTRT bit in the ADC_CR2 register to 1 (only applicable to regular channels).

After each conversion:
● If the regular channel group is
converted : — The last converted data is stored in the 16-bit ADC_DR register
— The EOC (end of conversion) flag is set to 1
— An interrupt is generated when the EOCIE bit is set

Tips

The injection channel cannot be switched continuously. The only exception in continuous mode is that the injection channel is configured to automatically switch after the regular channel (using the JAUTO bit), see section Automatic injection

08. Timing diagram

09. Scan mode

This mode is used to scan a group of analog channels.
Select the scan mode by setting the SCAN bit in the ADC_CR1 register to 1. After setting this bit to 1, the ADC will scan all channels selected in the ADC_SQRx register (for regular channels) or ADC_JSQR register (for injection channels). Perform a conversion for each channel in the group. After each conversion, the next channel in the group will be automatically converted. If the CONT bit is set to 1, the regular channel conversion will not stop at the last selected channel in the group, but will continue to convert from the first selected channel again.

If the DMA bit is set to 1, after each regular channel conversion, the direct memory access (DMA) controller is used to transfer the data converted from the regular channel group (stored in the ADC_DR register) to SRAM.

In the following cases, the EOC bit in the ADC_SR register is 1:
● If the EOCS bit is cleared, at the end of each rule group sequence conversion
● If the EOCS bit is 1,
the data converted from the injection channel at the end of each rule channel conversion is always Stored in the ADC_JDRx register.

10. Data alignment

The ALIGN bit in the ADC_CR2 register is used to select the alignment of the data stored after conversion. You can choose left-aligned and right-aligned, as shown in Figure 38 and Figure 39

The conversion data injected into the channel group will subtract the user-defined offset written in the ADC_JOFRx register, so the result can be a negative value. The SEXT bit represents the extended sign value.

For the channels in the rule group, no offset is subtracted, so only twelve bits are valid.

11. Register

11.1 ADC Status Register (ADC_SR)

ADC status register
offset address: 0x00
Reset value: 0x0000 0000

11.2 ADC Control Register 1 (ADC_CR1)

ADC control register 1
offset address: 0x04
reset value: 0x0000 0000

11.3 ADC Control Register 2 (ADC_CR2)

ADC control register 2
offset address: 0x08
reset value: 0x0000 0000

11.4 ADC sampling time register 1 (ADC_SMPR1)

ADC sample time register 1
offset address: 0x0C
reset value: 0x0000 0000

11.5 ADC sampling time register 2 (ADC_SMPR2)

ADC sample time register 2
offset address: 0x10
reset value: 0x0000 0000

11.6 ADC injection channel data offset register X (ADC_JOFRx) (x=1…4)

ADC injected channel data offset register x
offset address: 0x14-0x20
reset value: 0x0000 0000

11.7 ADC Watchdog High Threshold Register (ADC_HTR)

ADC watchdog higher threshold register
offset address: 0x24
Reset value: 0x0000 0FFF

11.8 ADC Watchdog Low Threshold Register (ADC_LTR)

ADC watchdog lower threshold register
offset address: 0x28
Reset value: 0x0000 0000

11.9 ADC Rule Sequence Register 1 (ADC_SQR1)

ADC regular sequence register 1
offset address: 0x2C
reset value: 0x0000 0000

11.10 ADC Rule Sequence Register 2 (ADC_SQR2)

ADC regular sequence register 2
offset address: 0x30
reset value: 0x0000 0000

11.11 ADC Rule Sequence Register 3 (ADC_SQR3)

ADC regular sequence register 3
offset address: 0x34
reset value: 0x0000 0000

11.12 ADC Injection Sequence Register (ADC_JSQR)

ADC injected sequence register
offset address: 0x38
Reset value: 0x0000 0000

11.13 ADC injection data register x (ADC_JDRx) (x = 1…4)

ADC injected data register x
offset address: 0x3C-0x48
Reset value: 0x0000 0000

11.14 ADC Rule Data Register (ADC_DR)

ADC regular data register
offset address: 0x4C
reset value: 0x0000 0000

11.15 ADC General Status Register (ADC_CSR)

ADC Common status register
offset address: 0x00 (the offset address is related to ADC1 base address + 0x300)
Reset value: 0x0000 0000
This register can provide status bit images of different ADCs. However, it is read-only and does not allow different status bits to be cleared. It must be written as 0 in the corresponding ADC_SR register to clear each status bit.

11.16 ADC General Control Register (ADC_CCR)

ADC common control register
offset address: 0x04 (the offset address is related to ADC1 base address + 0x300)
Reset value: 0x0000 0000

11.17 ADC general rule data register (ADC_CDR) applicable to dual and triple modes

ADC common regular data register for dual and triple modes
offset address: 0x08 (the offset address is related to ADC1 base address + 0x300)
reset value: 0x0000 0000

12. Appendix

12.1 [STM32] STM32 series tutorial summary

Website: [STM32] STM32 series tutorial summary

13. Statement

STM32F4xx English Reference Manual