STM32 Flash learning (1)

Introduction to STM32 FLASH

Different models of STM32 have different Flash capacities.
The FLASH capacity of the STM32F103RCT6 selected by the MiniSTM32 development board is 256K bytes, which is a large-capacity product.

The flash memory module of STM32 is composed of three parts: main memory, information block and flash memory interface register.

Main memory, this part is used to store code and data constants (such as const type data).
For high-capacity products, it is divided into 256 pages of 2K bytes each. Note that the small and medium capacity products only have 1K bytes per page.

The starting address of the main memory is 0X08000000. When both B0 and B1 are connected to GND, the code starts to run from 0X08000000.

Information block, this part is divided into 2 small parts, among which the startup program code is used to store the startup program that comes with ST, and is used to download the code through the serial port. When B0 is connected to V3.3 and B1 is connected to GND, the operation is this part of the code. The user selects the byte, which is generally used to configure functions such as write protection and read protection.

The flash memory interface register, which is used to control the reading and writing of the flash memory, is the control mechanism of the entire flash memory module.

Writing to the main memory and information blocks is managed by the embedded flash program/erase controller (FPEC); the high voltage for programming and erasing is internally generated.

When performing a flash write operation, any read operation to the flash memory will lock the bus, and the read operation can only be performed correctly after the write operation is completed;

Flash memory read

The built-in flash memory module can be directly addressed in the general address space, and any read operation of 32-bit data can access the contents of the flash memory module and obtain corresponding data.
The read interface includes a read controller on the flash side, and also includes an AHB interface to connect with the CPU.

Pay attention to the waiting time of the flash memory, because the CPU runs much faster than the FLASH, and the fastest access speed of the STM32F103's FLASH is ≤24MHz. If the CPU frequency exceeds this speed, the waiting time must be added.
For example, if we generally use a main frequency of 72MHz, then the FLASH waiting period must be set to 2, which is set through the FLASH_ACR register.

To read a halfword from address addr (halfword is 16 bits, word is 32 bits), you can read it with the following statement:

data = *(vu16*)addr;

Cast addr to a vu16 pointer, and then take the value of the address pointed to by the pointer to get the value of the addr address.
Change the above vu16 to vu8 to read a byte of the specified address.

Programming and Erasing of Flash

STM32 flash programming is handled by the FPEC (Flash Program and Erase Controller) module, which contains seven 32-bit registers, which are:

• FPEC key register (FLASH_KEYR)
• Option byte key register (FLASH_OPTKEYR)
• Flash Control Register (FLASH_CR)
• Flash Status Register (FLASH_SR)
• Flash Address Register (FLASH_AR)
• Select Byte Register (FLASH_OBR)
• Write Protection Register (FLASH_WRPR)

Among them, the FPEC key register has a total of 3 key values:
RDPRT key=0x000000A5
KEY1=0X45670123
KEY2=0XCDEF89AB

After the STM32 is reset, the FPEC module is protected and cannot be written to the FLASH_CR register;
the FPEC module can be opened by writing a specific sequence to the FLASH_KEYR register (that is, writing to KEY1 and KEY2), and we can only operate after the write protection is released. related registers.

The programming of STM32 flash memory must write 16 bits each time.
When the PG bit of the FLASH_CR register is 1, writing a halfword at a flash memory address will start a programming;
writing any non-halfword data, FPEC will generate a bus error. .
During the programming process (BSY bit is 1), any operation of reading and writing the flash memory will cause the CPU to suspend until the end of the flash memory programming.

Similarly, when programming the FLASH of STM32, it must also require that the FLASH of its write address is erased (its value must be 0xffff), otherwise it cannot be written, and a warning will be obtained in the PGERR bit of the FLASH_SR register.

• Check if the LOCK of FLASH_CR is unlocked, if not, unlock it first.
• Check the BSY bit of the FLASH_SR register to make sure there are no other programming operations in progress.
• Set the PG bit of the FLASH_CR register to 1.
• Write the halfword to be programmed at the specified address.
• Wait for the BSY bit to become 0.
• Read the written address and verify the data.

When programming the FLASH of STM32, first determine whether the abbreviated address is erased.
STM32 flash memory erase is divided into two types: page erase and chip erase.

• Check if the LOCK of FLASH_CR is unlocked, if not, unlock it first.
• Check the BSY bit of the FLASH_SR register to verify that no other flash operations are in progress.
• Set the PER bit of the FLASH_CR register to 1.
• Use the FLASH_AR register to select the page to be erased.
• Set the STRT bit of the FLASH_CR register to 1.
• Wait for the BSY bit to become 0.
• The erased page is read and verified.

Read and write related registers

FPEC key register: FLASH_KEYR.

All of these bits are write-only and return 0 when read.
Bit 31~0: FKEYR: FPEC key, these bits are used for the unlock key belonging to FPEC.
This register is mainly used to unlock FPEC, and the FLASH_CR register can only be written after the register is unlocked by writing a specific sequence (KEY1 and KEY2).

Flash Control Register: FLASH_CR.

• LOCK bit, this bit is used to indicate whether the FLASH_CR register is locked, and the hardware will clear it to zero after detecting the correct unlock sequence. After an unsuccessful unlock operation, this bit will not change until the next system reset.
• STRT bit, this bit is used to start an erase operation. Writing 1 to this bit will perform an erase operation.
• PER bit, this bit is used to select the page erase operation, when the page is erased, this bit needs to be set to 1.
• PG bit, this bit is used to select the programming operation, often when FLASH writes data, this bit needs to be set to 1.

Flash status register: FLASH_SR.

• EOP: End of operation, set to 1 by hardware and write 1 to clear whenever a flash operation (program/erase) is complete.
• WRPRERR: Write protection error, when programming the write-protected flash memory address, the hardware sets this bit to 1, and writing 1 can clear it.
• PDERR: programming error, when trying to program an address other than 0xffff, the hardware sets it to 1, and it can be cleared when writing 1. Before programming, clear the STRT bit of the FLASH_CR register.
• BSY: Busy, indicating that a flash operation is in progress. This bit is set to 1 when the flash operation starts and cleared to 0 when the operation ends or an error occurs.

Flash address register: FLASH_AR

These bits are modified by hardware to the current/last used address. During page erase, software must modify this register to specify the page to be erased.

Bit 31~0: FAR: Flash memory address, select the address to be programmed when programming, and select the page to be erased when performing page erase. When the BSY bit of FLASH_SR is 1, this register cannot be written.