STM32 learning manual (1) - STM32 Overview

First, what is?

Based Cortex-M3 core, using the ARMv7-M 32bitMCU architecture

Second, what can we do?

And related internal resources, such as communication interface

• The USART: ESP8266 the WIFI module, GSM module, a Bluetooth module, GPS module, a fingerprint identification module block like.

• IIC: EEPROM, MPU6050 gyroscope, 0.96-inch OLED screen, capacitive screens

• SPI: serial FLASH, Ethernet W5500, VS1003 / 1053 audio module, SPI interface OLED screen, resistive screens.

• AD / DA: photosensitive sensor module, the sensor module smoke, combustible gas sensor module, shown simplified wave or the like.

Third, the system structure

as the picture shows:

• Five drive units:

  　　　 ─ Cortex ™ -M3 core DCode bus (D-bus), and the system bus (S-bus)

　　　   ─ General DMA1 and General DMA2

　　　   ─ Ethernet DMA

• Three passive unit

 　　　  ─ internal SRAM

　　　   ─ internal flash memory

　　　   ─ AHB to APB bridge (AHB2APBx), which connects all the devices APB

This is done through a multi-level framework AHB bus connected to each other.

1. ICode bus: the kernel used to read the flash value
2. DCode bus: (a constant stored in the flash const modified) data interface with flash
3. System Bus: CortexM3 core system bus (peripheral bus) bus to the matrix, the matrix bus to coordinate access between the core and DMA.
4. DMA bus: The bus master DMA interface to the AHB bus matrix associated, coordinated with the CPU bus matrix and DMA DCode to access SRAM, flash memory, and peripherals.
5. Bus Matrix: Matrix coordination between the bus and the core system bus master DMA bus access arbitration, the use of rotation algorithms. In the interconnected products, the matrix contains 5 bus drive member (CPU of the DCode, a system bus, an Ethernet DMA, DMA1 and DMA2 bus bus) and from 3 parts (flash memory interface (FLITF), SRAM and AHB2APB bridge). In other products, comprising four drive bus matrix means (CPU of DCode, a system bus, DMA1 and DMA2 bus Bus) and four passive member (flash memory interface (FLITF), SRAM, FSMC and AHB2APB bridge). AHB bus matrix via peripheral bus connected to the system, allowed DMA access.
6. AHB / APB bridge: two AHB / APB bridge provides a synchronous connection between two AHB and the APB

Fourth, register

4GB storage space planning, a SECTOR divided into eight blocks, each block 512MB, address allocation by the chip company (Register Map)

• SRAM : 64KB
  
• flash：512K
• Piece out of 6,187,655
• FSMC of bank1 ~ bank2
• FSMC of bank3 ~ bank4
• FSMC register
• Reserved block
• Cortex-M3 internal peripherals

                         How to access the contents of the register?

• STM32 peripheral address mapping (direct configuration register)
• Packaging register with C (libraries)